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Merge pull request #360 from antonblanchard/log2ceil-issue

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wishbone_bram_wrapper ram_addr_bits is 1 bit off
This commit is contained in:
Michael Neuling
2022-03-18 18:28:34 +11:00
committed by GitHub
parent 30fd936c12 b5accb78b2
commit 8bf48ac094
1 changed files with 1 additions and 1 deletions
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wishbone_bram_wrapper.vhdl
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@@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
end entity wishbone_bram_wrapper;
architecture behaviour of wishbone_bram_wrapper is
constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;
-- RAM interface
signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);