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litedram: Add basic support for LiteX LiteDRAM

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This comes in two parts:

 - A generator script which uses LiteX to generate litedram cores
along with their init files for various boards (currently Arty and
Nexys-video). This comes with configs for arty and nexys_video.

 - A fusesoc "generator" which uses pre-generated litedram cores

The generation process is manual on purpose. This include pre-generated
cores for the two above boards.

This is done so that one doesn't have to install LiteX to build
microwatt. In addition, the generator script or wrapper vhdl tend to
break when LiteX changes significantly which happens.

This is still rather standalone and hasn't been plumbed into the SoC
or the FPGA toplevel files yet.

At this point LiteDRAM self-initializes using a built-in VexRiscv
"Minimum" core obtained from LiteX and included in this commit. There
is some plumbing to generate and cores that are initialized by Microwatt
directly but this isn't working yet and so isn't enabled yet.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2019-09-10 18:05:32 +01:00
parent 31b55b2a75
commit 982cf166dd
60 changed files with 58556 additions and 2 deletions
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5
scripts/mw_debug/Makefile
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@@ -5,3 +5,8 @@ all: mw_debug
mw_debug: mw_debug.c
$(CC) -o $@ $^ -lurjtag
clean:
rm -f mw_debug
distclean:
rm -f *~