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control: Reduce pipeline depth to 1

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To match our one stage execute.

This might change back if we end up adding 2 stages to match the
LSU, but in that case we'll want forwards as well.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2019-10-31 19:43:58 +11:00
parent cff4b13a9b
commit 98bd8b73c0
2 changed files with 5 additions and 5 deletions
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8
control.vhdl
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@@ -57,7 +57,7 @@ architecture rtl of control is
begin
gpr_hazard0: entity work.gpr_hazard
generic map (
PIPELINE_DEPTH => 2
PIPELINE_DEPTH => PIPELINE_DEPTH
)
port map (
clk => clk,
@@ -72,7 +72,7 @@ begin
gpr_hazard1: entity work.gpr_hazard
generic map (
PIPELINE_DEPTH => 2
PIPELINE_DEPTH => PIPELINE_DEPTH
)
port map (
clk => clk,
@@ -87,7 +87,7 @@ begin
gpr_hazard2: entity work.gpr_hazard
generic map (
PIPELINE_DEPTH => 2
PIPELINE_DEPTH => PIPELINE_DEPTH
)
port map (
clk => clk,
@@ -102,7 +102,7 @@ begin
cr_hazard0: entity work.cr_hazard
generic map (
PIPELINE_DEPTH => 2
PIPELINE_DEPTH => PIPELINE_DEPTH
)
port map (
clk => clk,

2
decode2.vhdl
View File

@@ -152,7 +152,7 @@ architecture behaviour of decode2 is
begin
control_0: entity work.control
generic map (
PIPELINE_DEPTH => 2
PIPELINE_DEPTH => 1
)
port map (
clk => clk,