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Don't use VHDL 2008 condition operator in multiply

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
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Anton Blanchard
2019-09-19 20:18:01 +10:00
committed by Anton Blanchard
parent 550b2b8608
commit 99dd4de54e
1 changed files with 1 additions and 1 deletions
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multiply.vhdl
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@@ -85,7 +85,7 @@ begin
m_out.write_reg_data <= d2;
m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
if v.multiply_pipeline(PIPELINE_DEPTH-1).valid then
if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
m_out.valid <= '1';
m_out.write_reg_enable <= '1';