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https://github.com/antonblanchard/microwatt.git
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core: Add support for single-precision FP loads and stores
This adds code to loadstore1 to convert between single-precision and double-precision formats, and implements the lfs* and stfs* instructions. The conversion processes are described in Power ISA v3.1 Book 1 sections 4.6.2 and 4.6.3. These conversions take one cycle, so lfs* and stfs* are one cycle slower than lfd* and stfd*. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
@@ -287,6 +287,7 @@ package common is
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virt_mode : std_ulogic; -- do translation through TLB
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priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
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mode_32bit : std_ulogic; -- trim addresses to 32 bits
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is_32bit : std_ulogic;
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end record;
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constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
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sign_extend => '0', update => '0', xerc => xerc_init,
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@@ -294,7 +295,7 @@ package common is
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nia => (others => '0'), insn => (others => '0'),
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addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'),
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write_reg => (others => '0'), length => (others => '0'),
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mode_32bit => '0', others => (others => '0'));
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mode_32bit => '0', is_32bit => '0', others => (others => '0'));
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type Loadstore1ToExecute1Type is record
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busy : std_ulogic;
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@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.helpers.all;
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entity zero_counter is
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port (
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@@ -15,42 +16,6 @@ entity zero_counter is
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end entity zero_counter;
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architecture behaviour of zero_counter is
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-- Reverse the order of bits in a word
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function bit_reverse(a: std_ulogic_vector) return std_ulogic_vector is
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variable ret: std_ulogic_vector(a'left downto a'right);
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begin
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for i in a'right to a'left loop
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ret(a'left + a'right - i) := a(i);
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end loop;
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return ret;
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end;
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-- If there is only one bit set in a doubleword, return its bit number
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-- (counting from the right). Each bit of the result is obtained by
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-- ORing together 32 bits of the input:
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-- bit 0 = a[1] or a[3] or a[5] or ...
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-- bit 1 = a[2] or a[3] or a[6] or a[7] or ...
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-- bit 2 = a[4..7] or a[12..15] or ...
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-- bit 5 = a[32..63] ORed together
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function bit_number(a: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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variable ret: std_ulogic_vector(5 downto 0);
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variable stride: natural;
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variable bit: std_ulogic;
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variable k: natural;
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begin
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stride := 2;
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for i in 0 to 5 loop
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bit := '0';
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for j in 0 to (64 / stride) - 1 loop
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k := j * stride;
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bit := bit or (or a(k + stride - 1 downto k + (stride / 2)));
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end loop;
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ret(i) := bit;
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stride := stride * 2;
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end loop;
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return ret;
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end;
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signal inp : std_ulogic_vector(63 downto 0);
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signal sum : std_ulogic_vector(64 downto 0);
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signal msb_r : std_ulogic;
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16
decode1.vhdl
16
decode1.vhdl
@@ -74,8 +74,8 @@ architecture behaviour of decode1 is
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35 => (LDST, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- lbzu
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50 => (LDST, OP_FPLOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- lfd
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51 => (LDST, OP_FPLOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- lfdu
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-- 48 => (LDST, OP_FPLOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- lfs
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-- 49 => (LDST, OP_FPLOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- lfsu
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48 => (LDST, OP_FPLOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- lfs
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49 => (LDST, OP_FPLOAD, RA_OR_ZERO, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- lfsu
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42 => (LDST, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0'), -- lha
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43 => (LDST, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '1', '0', '0', '0', NONE, '0', '0'), -- lhau
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40 => (LDST, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- lhz
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@@ -93,8 +93,8 @@ architecture behaviour of decode1 is
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39 => (LDST, OP_STORE, RA_OR_ZERO, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- stbu
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54 => (LDST, OP_FPSTORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- stfd
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55 => (LDST, OP_FPSTORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- stfdu
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-- 52 => (LDST, OP_FPSTORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- stfs
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-- 53 => (LDST, OP_FPSTORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- stfsu
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52 => (LDST, OP_FPSTORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- stfs
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53 => (LDST, OP_FPSTORE, RA_OR_ZERO, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- stfsu
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44 => (LDST, OP_STORE, RA_OR_ZERO, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- sth
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45 => (LDST, OP_STORE, RA_OR_ZERO, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- sthu
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36 => (LDST, OP_STORE, RA_OR_ZERO, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- stw
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@@ -284,8 +284,8 @@ architecture behaviour of decode1 is
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2#1001110111# => (LDST, OP_FPLOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- lfdux
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2#1101010111# => (LDST, OP_FPLOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0'), -- lfiwax
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2#1101110111# => (LDST, OP_FPLOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- lfiwzx
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-- 2#1000010111# => (LDST, OP_FPLOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- lfsx
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-- 2#1000110111# => (LDST, OP_FPLOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- lfsux
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2#1000010111# => (LDST, OP_FPLOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- lfsx
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2#1000110111# => (LDST, OP_FPLOAD, RA_OR_ZERO, RB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- lfsux
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2#0001110100# => (LDST, OP_LOAD, RA_OR_ZERO, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '1', '0', '0', NONE, '0', '0'), -- lharx
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2#0101110111# => (LDST, OP_LOAD, RA_OR_ZERO, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '1', '0', '0', '0', NONE, '0', '0'), -- lhaux
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2#0101010111# => (LDST, OP_LOAD, RA_OR_ZERO, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0'), -- lhax
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@@ -367,8 +367,8 @@ architecture behaviour of decode1 is
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2#1011010111# => (LDST, OP_FPSTORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- stfdx
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2#1011110111# => (LDST, OP_FPSTORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- stfdux
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2#1111010111# => (LDST, OP_FPSTORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- stfiwx
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-- 2#1010010111# => (LDST, OP_FPSTORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- stfsx
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-- 2#1010110111# => (LDST, OP_FPSTORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- stfsux
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2#1010010111# => (LDST, OP_FPSTORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0'), -- stfsx
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2#1010110111# => (LDST, OP_FPSTORE, RA_OR_ZERO, RB, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0'), -- stfsux
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2#1110010110# => (LDST, OP_STORE, RA_OR_ZERO, RB, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '1', '0', '0', '0', '0', '0', NONE, '0', '0'), -- sthbrx
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2#1110110101# => (LDST, OP_STORE, RA_OR_ZERO, RB, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- sthcix
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2#1011010110# => (LDST, OP_STORE, RA_OR_ZERO, RB, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '1', '0', '0', ONE, '0', '0'), -- sthcx
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@@ -1259,6 +1259,7 @@ begin
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lv.virt_mode := ctrl.msr(MSR_DR);
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lv.priv_mode := not ctrl.msr(MSR_PR);
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lv.mode_32bit := not ctrl.msr(MSR_SF);
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lv.is_32bit := e_in.is_32bit;
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-- Update registers
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rin <= v;
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53
helpers.vhdl
53
helpers.vhdl
@@ -25,6 +25,10 @@ package helpers is
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function byte_reverse(val: std_ulogic_vector(63 downto 0); size: integer) return std_ulogic_vector;
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function sign_extend(val: std_ulogic_vector(63 downto 0); size: natural) return std_ulogic_vector;
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function bit_reverse(a: std_ulogic_vector) return std_ulogic_vector;
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function bit_number(a: std_ulogic_vector(63 downto 0)) return std_ulogic_vector;
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function count_left_zeroes(val: std_ulogic_vector) return std_ulogic_vector;
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end package helpers;
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package body helpers is
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@@ -206,4 +210,53 @@ package body helpers is
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return std_ulogic_vector(ret);
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end;
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-- Reverse the order of bits in a word
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function bit_reverse(a: std_ulogic_vector) return std_ulogic_vector is
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variable ret: std_ulogic_vector(a'left downto a'right);
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begin
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for i in a'right to a'left loop
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ret(a'left + a'right - i) := a(i);
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end loop;
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return ret;
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end;
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-- If there is only one bit set in a doubleword, return its bit number
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-- (counting from the right). Each bit of the result is obtained by
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-- ORing together 32 bits of the input:
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-- bit 0 = a[1] or a[3] or a[5] or ...
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-- bit 1 = a[2] or a[3] or a[6] or a[7] or ...
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-- bit 2 = a[4..7] or a[12..15] or ...
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-- bit 5 = a[32..63] ORed together
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function bit_number(a: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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variable ret: std_ulogic_vector(5 downto 0);
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variable stride: natural;
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variable bit: std_ulogic;
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variable k: natural;
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begin
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stride := 2;
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for i in 0 to 5 loop
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bit := '0';
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for j in 0 to (64 / stride) - 1 loop
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k := j * stride;
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bit := bit or (or a(k + stride - 1 downto k + (stride / 2)));
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end loop;
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ret(i) := bit;
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stride := stride * 2;
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end loop;
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return ret;
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end;
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-- Count leading zeroes operation
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-- Assumes the value passed in is not zero (if it is, zero is returned)
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function count_left_zeroes(val: std_ulogic_vector) return std_ulogic_vector is
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variable rev: std_ulogic_vector(val'left downto val'right);
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variable sum: std_ulogic_vector(val'left downto val'right);
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variable onehot: std_ulogic_vector(val'left downto val'right);
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begin
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rev := bit_reverse(val);
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sum := std_ulogic_vector(- signed(rev));
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onehot := sum and rev;
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return bit_number(std_ulogic_vector(resize(unsigned(onehot), 64)));
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end;
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end package body helpers;
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210
loadstore1.vhdl
210
loadstore1.vhdl
@@ -45,10 +45,12 @@ architecture behave of loadstore1 is
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-- State machine for unaligned loads/stores
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type state_t is (IDLE, -- ready for instruction
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FPR_CONV, -- converting double to float for store
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SECOND_REQ, -- send 2nd request of unaligned xfer
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ACK_WAIT, -- waiting for ack from dcache
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MMU_LOOKUP, -- waiting for MMU to look up translation
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TLBIE_WAIT, -- waiting for MMU to finish doing a tlbie
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FINISH_LFS, -- write back converted SP data for lfs*
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COMPLETE -- extra cycle to complete an operation
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);
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@@ -89,6 +91,11 @@ architecture behave of loadstore1 is
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do_update : std_ulogic;
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extra_cycle : std_ulogic;
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mode_32bit : std_ulogic;
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load_sp : std_ulogic;
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ld_sp_data : std_ulogic_vector(31 downto 0);
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ld_sp_nz : std_ulogic;
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ld_sp_lz : std_ulogic_vector(5 downto 0);
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st_sp_data : std_ulogic_vector(31 downto 0);
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end record;
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type byte_sel_t is array(0 to 7) of std_ulogic;
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@@ -98,6 +105,9 @@ architecture behave of loadstore1 is
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signal r, rin : reg_stage_t;
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signal lsu_sum : std_ulogic_vector(63 downto 0);
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signal store_sp_data : std_ulogic_vector(31 downto 0);
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signal load_dp_data : std_ulogic_vector(63 downto 0);
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-- Generate byte enables from sizes
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function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
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begin
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@@ -128,6 +138,72 @@ architecture behave of loadstore1 is
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to_integer(unsigned(address))));
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end function xfer_data_sel;
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-- 23-bit right shifter for DP -> SP float conversions
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function shifter_23r(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
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return std_ulogic_vector is
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variable fs1 : std_ulogic_vector(22 downto 0);
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variable fs2 : std_ulogic_vector(22 downto 0);
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begin
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case shift(1 downto 0) is
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when "00" =>
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fs1 := frac;
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when "01" =>
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fs1 := '0' & frac(22 downto 1);
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when "10" =>
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fs1 := "00" & frac(22 downto 2);
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when others =>
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fs1 := "000" & frac(22 downto 3);
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end case;
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case shift(4 downto 2) is
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when "000" =>
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fs2 := fs1;
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when "001" =>
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fs2 := x"0" & fs1(22 downto 4);
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when "010" =>
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fs2 := x"00" & fs1(22 downto 8);
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when "011" =>
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fs2 := x"000" & fs1(22 downto 12);
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when "100" =>
|
||||
fs2 := x"0000" & fs1(22 downto 16);
|
||||
when others =>
|
||||
fs2 := x"00000" & fs1(22 downto 20);
|
||||
end case;
|
||||
return fs2;
|
||||
end;
|
||||
|
||||
-- 23-bit left shifter for SP -> DP float conversions
|
||||
function shifter_23l(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
|
||||
return std_ulogic_vector is
|
||||
variable fs1 : std_ulogic_vector(22 downto 0);
|
||||
variable fs2 : std_ulogic_vector(22 downto 0);
|
||||
begin
|
||||
case shift(1 downto 0) is
|
||||
when "00" =>
|
||||
fs1 := frac;
|
||||
when "01" =>
|
||||
fs1 := frac(21 downto 0) & '0';
|
||||
when "10" =>
|
||||
fs1 := frac(20 downto 0) & "00";
|
||||
when others =>
|
||||
fs1 := frac(19 downto 0) & "000";
|
||||
end case;
|
||||
case shift(4 downto 2) is
|
||||
when "000" =>
|
||||
fs2 := fs1;
|
||||
when "001" =>
|
||||
fs2 := fs1(18 downto 0) & x"0" ;
|
||||
when "010" =>
|
||||
fs2 := fs1(14 downto 0) & x"00";
|
||||
when "011" =>
|
||||
fs2 := fs1(10 downto 0) & x"000";
|
||||
when "100" =>
|
||||
fs2 := fs1(6 downto 0) & x"0000";
|
||||
when others =>
|
||||
fs2 := fs1(2 downto 0) & x"00000";
|
||||
end case;
|
||||
return fs2;
|
||||
end;
|
||||
|
||||
begin
|
||||
-- Calculate the address in the first cycle
|
||||
lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
|
||||
@@ -145,6 +221,59 @@ begin
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ls_fp_conv: if HAS_FPU generate
|
||||
-- Convert DP data to SP for stfs
|
||||
dp_to_sp: process(all)
|
||||
variable exp : unsigned(10 downto 0);
|
||||
variable frac : std_ulogic_vector(22 downto 0);
|
||||
variable shift : unsigned(4 downto 0);
|
||||
begin
|
||||
store_sp_data(31) <= l_in.data(63);
|
||||
store_sp_data(30 downto 0) <= (others => '0');
|
||||
exp := unsigned(l_in.data(62 downto 52));
|
||||
if exp > 896 then
|
||||
store_sp_data(30) <= l_in.data(62);
|
||||
store_sp_data(29 downto 0) <= l_in.data(58 downto 29);
|
||||
elsif exp >= 874 then
|
||||
-- denormalization required
|
||||
frac := '1' & l_in.data(51 downto 30);
|
||||
shift := 0 - exp(4 downto 0);
|
||||
store_sp_data(22 downto 0) <= shifter_23r(frac, shift);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Convert SP data to DP for lfs
|
||||
sp_to_dp: process(all)
|
||||
variable exp : unsigned(7 downto 0);
|
||||
variable exp_dp : unsigned(10 downto 0);
|
||||
variable exp_nz : std_ulogic;
|
||||
variable exp_ao : std_ulogic;
|
||||
variable frac : std_ulogic_vector(22 downto 0);
|
||||
variable frac_shift : unsigned(4 downto 0);
|
||||
begin
|
||||
frac := r.ld_sp_data(22 downto 0);
|
||||
exp := unsigned(r.ld_sp_data(30 downto 23));
|
||||
exp_nz := or (r.ld_sp_data(30 downto 23));
|
||||
exp_ao := and (r.ld_sp_data(30 downto 23));
|
||||
frac_shift := (others => '0');
|
||||
if exp_ao = '1' then
|
||||
exp_dp := to_unsigned(2047, 11); -- infinity or NaN
|
||||
elsif exp_nz = '1' then
|
||||
exp_dp := 896 + resize(exp, 11); -- finite normalized value
|
||||
elsif r.ld_sp_nz = '0' then
|
||||
exp_dp := to_unsigned(0, 11); -- zero
|
||||
else
|
||||
-- denormalized SP operand, need to normalize
|
||||
exp_dp := 896 - resize(unsigned(r.ld_sp_lz), 11);
|
||||
frac_shift := unsigned(r.ld_sp_lz(4 downto 0)) + 1;
|
||||
end if;
|
||||
load_dp_data(63) <= r.ld_sp_data(31);
|
||||
load_dp_data(62 downto 52) <= std_ulogic_vector(exp_dp);
|
||||
load_dp_data(51 downto 29) <= shifter_23l(frac, frac_shift);
|
||||
load_dp_data(28 downto 0) <= (others => '0');
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
loadstore1_1: process(all)
|
||||
variable v : reg_stage_t;
|
||||
variable brev_lenm1 : unsigned(2 downto 0);
|
||||
@@ -165,6 +294,9 @@ begin
|
||||
variable data_permuted : std_ulogic_vector(63 downto 0);
|
||||
variable data_trimmed : std_ulogic_vector(63 downto 0);
|
||||
variable store_data : std_ulogic_vector(63 downto 0);
|
||||
variable data_in : std_ulogic_vector(63 downto 0);
|
||||
variable byte_rev : std_ulogic;
|
||||
variable length : std_ulogic_vector(3 downto 0);
|
||||
variable use_second : byte_sel_t;
|
||||
variable trim_ctl : trim_ctl_t;
|
||||
variable negative : std_ulogic;
|
||||
@@ -176,6 +308,8 @@ begin
|
||||
variable mmu_mtspr : std_ulogic;
|
||||
variable itlb_fault : std_ulogic;
|
||||
variable misaligned : std_ulogic;
|
||||
variable fp_reg_conv : std_ulogic;
|
||||
variable lfs_done : std_ulogic;
|
||||
begin
|
||||
v := r;
|
||||
req := '0';
|
||||
@@ -185,8 +319,10 @@ begin
|
||||
sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
|
||||
dsisr := (others => '0');
|
||||
mmureq := '0';
|
||||
fp_reg_conv := '0';
|
||||
|
||||
write_enable := '0';
|
||||
lfs_done := '0';
|
||||
|
||||
do_update := r.do_update;
|
||||
v.do_update := '0';
|
||||
@@ -245,19 +381,38 @@ begin
|
||||
end case;
|
||||
end loop;
|
||||
|
||||
-- Byte reversing and rotating for stores
|
||||
-- Done in the first cycle (when l_in.valid = 1)
|
||||
if HAS_FPU then
|
||||
-- Single-precision FP conversion
|
||||
v.st_sp_data := store_sp_data;
|
||||
v.ld_sp_data := data_trimmed(31 downto 0);
|
||||
v.ld_sp_nz := or (data_trimmed(22 downto 0));
|
||||
v.ld_sp_lz := count_left_zeroes(data_trimmed(22 downto 0));
|
||||
end if;
|
||||
|
||||
-- Byte reversing and rotating for stores.
|
||||
-- Done in the first cycle (when l_in.valid = 1) for integer stores
|
||||
-- and DP float stores, and in the second cycle for SP float stores.
|
||||
store_data := r.store_data;
|
||||
if l_in.valid = '1' then
|
||||
byte_offset := unsigned(lsu_sum(2 downto 0));
|
||||
if l_in.valid = '1' or (HAS_FPU and r.state = FPR_CONV) then
|
||||
if HAS_FPU and r.state = FPR_CONV then
|
||||
data_in := x"00000000" & r.st_sp_data;
|
||||
byte_offset := unsigned(r.addr(2 downto 0));
|
||||
byte_rev := r.byte_reverse;
|
||||
length := r.length;
|
||||
else
|
||||
data_in := l_in.data;
|
||||
byte_offset := unsigned(lsu_sum(2 downto 0));
|
||||
byte_rev := l_in.byte_reverse;
|
||||
length := l_in.length;
|
||||
end if;
|
||||
brev_lenm1 := "000";
|
||||
if l_in.byte_reverse = '1' then
|
||||
brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
|
||||
if byte_rev = '1' then
|
||||
brev_lenm1 := unsigned(length(2 downto 0)) - 1;
|
||||
end if;
|
||||
for i in 0 to 7 loop
|
||||
k := (to_unsigned(i, 3) - byte_offset) xor brev_lenm1;
|
||||
j := to_integer(k) * 8;
|
||||
store_data(i * 8 + 7 downto i * 8) := l_in.data(j + 7 downto j);
|
||||
store_data(i * 8 + 7 downto i * 8) := data_in(j + 7 downto j);
|
||||
end loop;
|
||||
end if;
|
||||
v.store_data := store_data;
|
||||
@@ -292,6 +447,14 @@ begin
|
||||
case r.state is
|
||||
when IDLE =>
|
||||
|
||||
when FPR_CONV =>
|
||||
req := '1';
|
||||
if r.second_bytes /= "00000000" then
|
||||
v.state := SECOND_REQ;
|
||||
else
|
||||
v.state := ACK_WAIT;
|
||||
end if;
|
||||
|
||||
when SECOND_REQ =>
|
||||
req := '1';
|
||||
v.state := ACK_WAIT;
|
||||
@@ -323,8 +486,13 @@ begin
|
||||
v.load_data := data_permuted;
|
||||
end if;
|
||||
else
|
||||
write_enable := r.load;
|
||||
if r.extra_cycle = '1' then
|
||||
write_enable := r.load and not r.load_sp;
|
||||
if HAS_FPU and r.load_sp = '1' then
|
||||
-- SP to DP conversion takes a cycle
|
||||
-- Write back rA update in this cycle if needed
|
||||
do_update := r.update;
|
||||
v.state := FINISH_LFS;
|
||||
elsif r.extra_cycle = '1' then
|
||||
-- loads with rA update need an extra cycle
|
||||
v.state := COMPLETE;
|
||||
v.do_update := r.update;
|
||||
@@ -362,6 +530,9 @@ begin
|
||||
|
||||
when TLBIE_WAIT =>
|
||||
|
||||
when FINISH_LFS =>
|
||||
lfs_done := '1';
|
||||
|
||||
when COMPLETE =>
|
||||
exception := r.align_intr;
|
||||
|
||||
@@ -395,6 +566,7 @@ begin
|
||||
v.nc := l_in.ci;
|
||||
v.virt_mode := l_in.virt_mode;
|
||||
v.priv_mode := l_in.priv_mode;
|
||||
v.load_sp := '0';
|
||||
v.wait_dcache := '0';
|
||||
v.wait_mmu := '0';
|
||||
v.do_update := '0';
|
||||
@@ -436,14 +608,24 @@ begin
|
||||
v.dcbz := '1';
|
||||
when OP_FPSTORE =>
|
||||
if HAS_FPU then
|
||||
req := '1';
|
||||
if l_in.is_32bit = '1' then
|
||||
v.state := FPR_CONV;
|
||||
fp_reg_conv := '1';
|
||||
else
|
||||
req := '1';
|
||||
end if;
|
||||
end if;
|
||||
when OP_FPLOAD =>
|
||||
if HAS_FPU then
|
||||
v.load := '1';
|
||||
req := '1';
|
||||
-- Allow an extra cycle for RA update
|
||||
-- Allow an extra cycle for SP->DP precision conversion
|
||||
-- or RA update
|
||||
v.extra_cycle := l_in.update;
|
||||
if l_in.is_32bit = '1' then
|
||||
v.load_sp := '1';
|
||||
v.extra_cycle := '1';
|
||||
end if;
|
||||
end if;
|
||||
when OP_TLBIE =>
|
||||
mmureq := '1';
|
||||
@@ -500,7 +682,7 @@ begin
|
||||
end if;
|
||||
end if;
|
||||
|
||||
v.busy := req or mmureq or mmu_mtspr;
|
||||
v.busy := req or mmureq or mmu_mtspr or fp_reg_conv;
|
||||
end if;
|
||||
|
||||
-- Update outputs to dcache
|
||||
@@ -539,6 +721,10 @@ begin
|
||||
l_out.write_enable <= '1';
|
||||
l_out.write_reg <= gpr_to_gspr(r.update_reg);
|
||||
l_out.write_data <= r.addr;
|
||||
elsif lfs_done = '1' then
|
||||
l_out.write_enable <= '1';
|
||||
l_out.write_reg <= r.write_reg;
|
||||
l_out.write_data <= load_dp_data;
|
||||
else
|
||||
l_out.write_enable <= write_enable;
|
||||
l_out.write_reg <= r.write_reg;
|
||||
|
||||
Reference in New Issue
Block a user