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FPU: Clear FPSCR[FR,FI] on overflow in convert-to-integer instructions

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Also simplify INT_CHECK state by going to INT_OFLOW on overflow.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
2025-12-11 09:19:12 +11:00
parent 37edba4da7
commit 9f27f60b26
1 changed files with 3 additions and 7 deletions
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10
fpu.vhdl
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@@ -2377,26 +2377,22 @@ begin
else
msb := r.r(63);
end if;
opsel_r <= RES_MISC;
misc_sel <= "110";
if (r.insn(8) = '0' and msb /= r.result_sign) or
(r.insn(8) = '1' and msb /= '1') then
set_r := '1';
v.fpscr(FPSCR_VXCVI) := '1';
invalid := '1';
v.state := INT_OFLOW;
else
set_r := '0';
if r.fpscr(FPSCR_FI) = '1' then
v.fpscr(FPSCR_XX) := '1';
end if;
arith_done := '1';
end if;
arith_done := '1';
when INT_OFLOW =>
opsel_r <= RES_MISC;
misc_sel <= "110";
set_r := '1';
v.fpscr(FPSCR_VXCVI) := '1';
v.fpscr(FPSCR_FR downto FPSCR_FI) := "00";
invalid := '1';
arith_done := '1';