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Code Releases Activity

No need to set HAS_FPU and LOG_LENGTH in Makefile

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This commit is contained in:
Anton Blanchard
2020-12-16 10:51:38 +11:00
committed by Anton Blanchard
parent 84f24a4773
commit a9a8bee920
2 changed files with 3 additions and 3 deletions
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4
Makefile
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@@ -116,7 +116,7 @@ $(soc_dram_tbs):
else
VERILATOR_CFLAGS=-O3
VERILATOR_FLAGS=-O3
VERILATOR_FLAGS=-O3 --x-assign=1 --x-initial=1
verilated_dram: litedram/generated/sim/litedram_core.v
verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
@@ -171,7 +171,7 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
endif
GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gLOG_LENGTH=8 -gHAS_FPU=false
-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
clkgen=fpga/clk_gen_ecp5.vhd
toplevel=fpga/top-generic.vhdl

2
fpga/top-caravel.vhdl
View File

@@ -18,7 +18,7 @@ entity toplevel is
SPI_FLASH_OFFSET : integer := 0;
SPI_FLASH_DEF_CKDV : natural := 4;
SPI_FLASH_DEF_QUAD : boolean := false;
LOG_LENGTH : natural := 16;
LOG_LENGTH : natural := 8;
UART_IS_16550 : boolean := true;
HAS_UART1 : boolean := false;
HAS_JTAG : boolean := true