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Merge pull request #311 from antonblanchard/litesdcard-nexys-video

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Update litesdcard from upstream and add Nexys Video support
This commit is contained in:
Michael Neuling 2021-08-11 09:48:07 +10:00 committed by GitHub
commit aa4e4e77c4
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GPG Key ID: 4AEE18F83AFDEB23
7 changed files with 320 additions and 124 deletions
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16
fpga/nexys-video.xdc
View File

@ -41,6 +41,22 @@ set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { spi_flas
set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
################################################################################
# SD card
################################################################################
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }]
set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_cmd }]
set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[0] }]
set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[1] }]
set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[2] }]
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[3] }]
set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sdcard_reset }]
# Put registers into IOBs to improve timing
set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdcard_*}]
################################################################################
# Ethernet (generated by LiteX)
################################################################################

143
fpga/top-nexys-video.vhdl
View File

@ -24,7 +24,8 @@ entity toplevel is
SPI_FLASH_DEF_QUAD : boolean := true;
LOG_LENGTH : natural := 2048;
UART_IS_16550 : boolean := true;
USE_LITEETH : boolean := false
USE_LITEETH : boolean := false;
USE_LITESDCARD : boolean := false
);
port(
ext_clk : in std_ulogic;
@ -63,6 +64,13 @@ entity toplevel is
eth_tx_ctl : out std_ulogic;
eth_tx_data : out std_ulogic_vector(3 downto 0);
-- SD card
sdcard_data : inout std_ulogic_vector(3 downto 0);
sdcard_cmd : inout std_ulogic;
sdcard_clk : out std_ulogic;
sdcard_cd : in std_ulogic;
sdcard_reset : out std_ulogic;
-- DRAM wires
ddram_a : out std_logic_vector(14 downto 0);
ddram_ba : out std_logic_vector(2 downto 0);
@ -97,6 +105,7 @@ architecture behaviour of toplevel is
signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic;
signal wb_ext_is_eth : std_ulogic;
signal wb_ext_is_sdcard : std_ulogic;
-- DRAM main data wishbone connection
signal wb_dram_in : wishbone_master_out;
@ -109,6 +118,16 @@ architecture behaviour of toplevel is
signal ext_irq_eth : std_ulogic;
signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
-- LiteSDCard connection
signal ext_irq_sdcard : std_ulogic := '0';
signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
signal wb_sddma_in : wb_io_slave_out;
signal wb_sddma_nr : wb_io_master_out;
signal wb_sddma_ir : wb_io_slave_out;
-- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic;
-- Control/status
signal core_alt_reset : std_ulogic;
@ -162,7 +181,8 @@ begin
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
LOG_LENGTH => LOG_LENGTH,
UART0_IS_16550 => UART_IS_16550,
HAS_LITEETH => USE_LITEETH
HAS_LITEETH => USE_LITEETH,
HAS_SD_CARD => USE_LITESDCARD
)
port map (
-- System signals
@ -182,8 +202,9 @@ begin
-- External interrupts
ext_irq_eth => ext_irq_eth,
ext_irq_sdcard => ext_irq_sdcard,
-- DRAM wishbone
-- IO wishbone
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_ext_io_in => wb_ext_io_in,
@ -191,6 +212,12 @@ begin
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init,
wb_ext_is_eth => wb_ext_is_eth,
wb_ext_is_sdcard => wb_ext_is_sdcard,
-- DMA wishbone
wishbone_dma_in => wb_sddma_in,
wishbone_dma_out => wb_sddma_out,
alt_reset => core_alt_reset
);
@ -428,8 +455,118 @@ begin
ext_irq_eth <= '0';
end generate;
-- SD card
has_sdcard : if USE_LITESDCARD generate
component litesdcard_core port (
clk : in std_ulogic;
rst : in std_ulogic;
-- wishbone for accessing control registers
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
wb_ctrl_cyc : in std_ulogic;
wb_ctrl_stb : in std_ulogic;
wb_ctrl_ack : out std_ulogic;
wb_ctrl_we : in std_ulogic;
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
wb_ctrl_err : out std_ulogic;
-- wishbone for SD card core to use for DMA
wb_dma_adr : out std_ulogic_vector(29 downto 0);
wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
wb_dma_sel : out std_ulogic_vector(3 downto 0);
wb_dma_cyc : out std_ulogic;
wb_dma_stb : out std_ulogic;
wb_dma_ack : in std_ulogic;
wb_dma_we : out std_ulogic;
wb_dma_cti : out std_ulogic_vector(2 downto 0);
wb_dma_bte : out std_ulogic_vector(1 downto 0);
wb_dma_err : in std_ulogic;
-- connections to SD card
sdcard_data : inout std_ulogic_vector(3 downto 0);
sdcard_cmd : inout std_ulogic;
sdcard_clk : out std_ulogic;
sdcard_cd : in std_ulogic;
irq : out std_ulogic
);
end component;
signal wb_sdcard_cyc : std_ulogic;
signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
begin
litesdcard : litesdcard_core
port map (
clk => system_clk,
rst => soc_rst,
wb_ctrl_adr => wb_sdcard_adr,
wb_ctrl_dat_w => wb_ext_io_in.dat,
wb_ctrl_dat_r => wb_sdcard_out.dat,
wb_ctrl_sel => wb_ext_io_in.sel,
wb_ctrl_cyc => wb_sdcard_cyc,
wb_ctrl_stb => wb_ext_io_in.stb,
wb_ctrl_ack => wb_sdcard_out.ack,
wb_ctrl_we => wb_ext_io_in.we,
wb_ctrl_cti => "000",
wb_ctrl_bte => "00",
wb_ctrl_err => open,
wb_dma_adr => wb_sddma_nr.adr,
wb_dma_dat_w => wb_sddma_nr.dat,
wb_dma_dat_r => wb_sddma_ir.dat,
wb_dma_sel => wb_sddma_nr.sel,
wb_dma_cyc => wb_sddma_nr.cyc,
wb_dma_stb => wb_sddma_nr.stb,
wb_dma_ack => wb_sddma_ir.ack,
wb_dma_we => wb_sddma_nr.we,
wb_dma_cti => open,
wb_dma_bte => open,
wb_dma_err => '0',
sdcard_data => sdcard_data,
sdcard_cmd => sdcard_cmd,
sdcard_clk => sdcard_clk,
sdcard_cd => sdcard_cd,
irq => ext_irq_sdcard
);
-- Gate cyc with chip select from SoC
wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(15 downto 2);
wb_sdcard_out.stall <= not wb_sdcard_out.ack;
sdcard_reset <= '0';
-- Convert non-pipelined DMA wishbone to pipelined by suppressing
-- non-acknowledged strobes
process(system_clk)
begin
if rising_edge(system_clk) then
wb_sddma_out <= wb_sddma_nr;
if wb_sddma_stb_sent = '1' or
(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
wb_sddma_out.stb <= '0';
end if;
if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
wb_sddma_stb_sent <= '0';
elsif wb_sddma_in.stall = '0' then
wb_sddma_stb_sent <= wb_sddma_nr.stb;
end if;
wb_sddma_ir <= wb_sddma_in;
end if;
end process;
end generate;
no_sdcard : if not USE_LITESDCARD generate
sdcard_reset <= '1';
end generate;
-- Mux WB response on the IO bus
wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
wb_sdcard_out when wb_ext_is_sdcard = '1' else
wb_dram_ctrl_out;
led4 <= system_clk_locked;

6
litesdcard/fusesoc-add-files.py
View File

@ -6,13 +6,13 @@ import pathlib
class LiteSDCardGenerator(Generator):
def run(self):
board = self.config.get('board')
vendor = self.config.get('vendor')
# Collect a bunch of directory path
script_dir = os.path.dirname(sys.argv[0])
gen_dir = os.path.join(script_dir, "generated", board)
gen_dir = os.path.join(script_dir, "generated", vendor)
print("Adding LiteSDCard for board... ", board)
print("Adding LiteSDCard for vendor... ", vendor)
# Add files to fusesoc
files = []

11
litesdcard/gen-src/generate.sh
View File

@ -1,6 +1,6 @@
#!/bin/bash
TARGETS=arty
VENDORS="xilinx"
ME=$(realpath $0)
echo ME=$ME
@ -13,12 +13,7 @@ mkdir -p $BUILD_PATH
GEN_PATH=$PARENT_PATH/generated
mkdir -p $GEN_PATH
# Note litesdcard/gen.py doesn't parse a YAML file, instead it takes
# a --vendor=xxx parameter, where xxx = xilinx or lattice. If we
# want to generate litesdcard for ecp5 we'll have to invent a way to
# map arty to xilinx and ecp5 to lattice
for i in $TARGETS
for i in $VENDORS
do
TARGET_BUILD_PATH=$BUILD_PATH/$i
TARGET_GEN_PATH=$GEN_PATH/$i
@ -28,7 +23,7 @@ do
mkdir -p $TARGET_GEN_PATH
echo "Generating $i in $TARGET_BUILD_PATH"
(cd $TARGET_BUILD_PATH && litesdcard_gen)
(cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i)
cp $TARGET_BUILD_PATH/build/gateware/litesdcard_core.v $TARGET_GEN_PATH/
done

253
litesdcard/generated/arty/litesdcard_core.v → litesdcard/generated/xilinx/litesdcard_core.v
View File

@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (3ffd64c) & LiteX (b55af215) on 2021-04-22 14:46:05
// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-10 08:40:47
//--------------------------------------------------------------------------------
module litesdcard_core(
input wire clk,
@ -37,14 +37,15 @@ wire sys_clk;
wire sys_rst;
wire por_clk;
reg int_rst = 1'd1;
reg reset_storage = 1'd0;
reg soc_rst = 1'd0;
wire cpu_rst;
reg [1:0] reset_storage = 2'd0;
reg reset_re = 1'd0;
reg [31:0] scratch_storage = 32'd305419896;
reg scratch_re = 1'd0;
wire [31:0] bus_errors_status;
wire bus_errors_we;
reg bus_errors_re = 1'd0;
wire reset;
reg bus_error = 1'd0;
reg [31:0] bus_errors = 32'd0;
wire [29:0] wb_ctrl_adr_1;
@ -573,13 +574,15 @@ wire sdblock2mem_fifo_source_ready;
wire sdblock2mem_fifo_source_first;
wire sdblock2mem_fifo_source_last;
wire [7:0] sdblock2mem_fifo_source_payload_data;
wire sdblock2mem_fifo_re;
reg sdblock2mem_fifo_readable = 1'd0;
wire sdblock2mem_fifo_syncfifo_we;
wire sdblock2mem_fifo_syncfifo_writable;
wire sdblock2mem_fifo_syncfifo_re;
wire sdblock2mem_fifo_syncfifo_readable;
wire [9:0] sdblock2mem_fifo_syncfifo_din;
wire [9:0] sdblock2mem_fifo_syncfifo_dout;
reg [9:0] sdblock2mem_fifo_level = 10'd0;
reg [9:0] sdblock2mem_fifo_level0 = 10'd0;
reg sdblock2mem_fifo_replace = 1'd0;
reg [8:0] sdblock2mem_fifo_produce = 9'd0;
reg [8:0] sdblock2mem_fifo_consume = 9'd0;
@ -590,6 +593,8 @@ wire [9:0] sdblock2mem_fifo_wrport_dat_w;
wire sdblock2mem_fifo_do_read;
wire [8:0] sdblock2mem_fifo_rdport_adr;
wire [9:0] sdblock2mem_fifo_rdport_dat_r;
wire sdblock2mem_fifo_rdport_re;
wire [9:0] sdblock2mem_fifo_level1;
wire [7:0] sdblock2mem_fifo_fifo_in_payload_data;
wire sdblock2mem_fifo_fifo_in_first;
wire sdblock2mem_fifo_fifo_in_last;
@ -720,13 +725,15 @@ wire sdmem2block_fifo_source_ready;
wire sdmem2block_fifo_source_first;
wire sdmem2block_fifo_source_last;
wire [7:0] sdmem2block_fifo_source_payload_data;
wire sdmem2block_fifo_re;
reg sdmem2block_fifo_readable = 1'd0;
wire sdmem2block_fifo_syncfifo_we;
wire sdmem2block_fifo_syncfifo_writable;
wire sdmem2block_fifo_syncfifo_re;
wire sdmem2block_fifo_syncfifo_readable;
wire [9:0] sdmem2block_fifo_syncfifo_din;
wire [9:0] sdmem2block_fifo_syncfifo_dout;
reg [9:0] sdmem2block_fifo_level = 10'd0;
reg [9:0] sdmem2block_fifo_level0 = 10'd0;
reg sdmem2block_fifo_replace = 1'd0;
reg [8:0] sdmem2block_fifo_produce = 9'd0;
reg [8:0] sdmem2block_fifo_consume = 9'd0;
@ -737,6 +744,8 @@ wire [9:0] sdmem2block_fifo_wrport_dat_w;
wire sdmem2block_fifo_do_read;
wire [8:0] sdmem2block_fifo_rdport_adr;
wire [9:0] sdmem2block_fifo_rdport_dat_r;
wire sdmem2block_fifo_rdport_re;
wire [9:0] sdmem2block_fifo_level1;
wire [7:0] sdmem2block_fifo_fifo_in_payload_data;
wire sdmem2block_fifo_fifo_in_first;
wire sdmem2block_fifo_fifo_in_last;
@ -894,9 +903,9 @@ wire litesdcardcore_interface0_bank_bus_we;
wire [31:0] litesdcardcore_interface0_bank_bus_dat_w;
reg [31:0] litesdcardcore_interface0_bank_bus_dat_r = 32'd0;
reg litesdcardcore_csrbank0_reset0_re = 1'd0;
wire litesdcardcore_csrbank0_reset0_r;
wire [1:0] litesdcardcore_csrbank0_reset0_r;
reg litesdcardcore_csrbank0_reset0_we = 1'd0;
wire litesdcardcore_csrbank0_reset0_w;
wire [1:0] litesdcardcore_csrbank0_reset0_w;
reg litesdcardcore_csrbank0_scratch0_re = 1'd0;
wire [31:0] litesdcardcore_csrbank0_scratch0_r;
reg litesdcardcore_csrbank0_scratch0_we = 1'd0;
@ -1133,15 +1142,14 @@ assign sdmem2block_source_source_ready0 = sdcore_sink_sink_ready0;
assign sdcore_sink_sink_first0 = sdmem2block_source_source_first0;
assign sdcore_sink_sink_last0 = sdmem2block_source_source_last0;
assign sdcore_sink_sink_payload_data0 = sdmem2block_source_source_payload_data0;
assign card_detect_trigger = card_detect_irq;
assign block2mem_dma_trigger = sdblock2mem_irq;
assign mem2block_dma_trigger = sdmem2block_irq;
assign card_detect_trigger = card_detect_irq;
assign cmd_done_trigger = sdcore_csrfield_done0;
assign irq = sdirq_irq;
assign sys_clk = clk;
assign por_clk = clk;
assign sys_rst = int_rst;
assign reset = reset_re;
assign bus_errors_status = bus_errors;
assign card_detect_status0 = sdcard_cd;
assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk);
@ -1211,13 +1219,13 @@ always @(*) begin
end
assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched);
always @(*) begin
subfragments_sdphyinit_next_state <= 1'd0;
init_count_sdphyinit_next_value <= 8'd0;
init_count_sdphyinit_next_value_ce <= 1'd0;
init_pads_out_payload_clk <= 1'd0;
init_pads_out_payload_cmd_o <= 1'd0;
init_pads_out_payload_cmd_oe <= 1'd0;
subfragments_sdphyinit_next_state <= 1'd0;
init_count_sdphyinit_next_value <= 8'd0;
init_pads_out_payload_data_o <= 4'd0;
init_count_sdphyinit_next_value_ce <= 1'd0;
init_pads_out_payload_data_oe <= 1'd0;
subfragments_sdphyinit_next_state <= subfragments_sdphyinit_state;
case (subfragments_sdphyinit_state)
@ -1246,13 +1254,13 @@ always @(*) begin
end
always @(*) begin
cmdw_done <= 1'd0;
subfragments_sdphycmdw_next_state <= 2'd0;
cmdw_pads_out_payload_clk <= 1'd0;
cmdw_count_sdphycmdw_next_value <= 8'd0;
cmdw_count_sdphycmdw_next_value_ce <= 1'd0;
cmdw_pads_out_payload_cmd_o <= 1'd0;
cmdw_pads_out_payload_cmd_oe <= 1'd0;
cmdw_sink_ready <= 1'd0;
subfragments_sdphycmdw_next_state <= 2'd0;
cmdw_count_sdphycmdw_next_value <= 8'd0;
cmdw_count_sdphycmdw_next_value_ce <= 1'd0;
subfragments_sdphycmdw_next_state <= subfragments_sdphycmdw_state;
case (subfragments_sdphycmdw_state)
1'd1: begin
@ -1356,24 +1364,24 @@ assign cmdr_cmdr_converter_source_valid = cmdr_cmdr_converter_strobe_all;
assign cmdr_cmdr_converter_load_part = (cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready);
assign cmdr_cmdr_buf_sink_ready = ((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready);
always @(*) begin
cmdr_pads_out_payload_clk <= 1'd0;
cmdr_pads_out_payload_cmd_o <= 1'd0;
cmdr_pads_out_payload_cmd_oe <= 1'd0;
cmdr_cmdr_source_source_ready0 <= 1'd0;
subfragments_sdphycmdr_next_state <= 3'd0;
cmdr_sink_ready <= 1'd0;
cmdr_timeout_sdphycmdr_next_value0 <= 32'd0;
cmdr_pads_out_payload_clk <= 1'd0;
cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0;
cmdr_pads_out_payload_cmd_o <= 1'd0;
cmdr_count_sdphycmdr_next_value1 <= 8'd0;
cmdr_pads_out_payload_cmd_oe <= 1'd0;
cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0;
cmdr_source_valid <= 1'd0;
cmdr_cmdr_source_source_ready0 <= 1'd0;
cmdr_busy_sdphycmdr_next_value2 <= 1'd0;
cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0;
cmdr_sink_ready <= 1'd0;
cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0;
cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0;
cmdr_source_valid <= 1'd0;
cmdr_source_last <= 1'd0;
cmdr_source_payload_data <= 8'd0;
cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0;
cmdr_source_payload_status <= 3'd0;
cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0;
subfragments_sdphycmdr_next_state <= subfragments_sdphycmdr_state;
case (subfragments_sdphycmdr_state)
1'd1: begin
@ -1519,23 +1527,23 @@ assign dataw_crc_converter_source_valid = dataw_crc_converter_strobe_all;
assign dataw_crc_converter_load_part = (dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready);
assign dataw_crc_buf_sink_ready = ((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready);
always @(*) begin
dataw_count_sdphydataw_next_value_ce3 <= 1'd0;
dataw_pads_out_payload_clk <= 1'd0;
dataw_crc_reset <= 1'd0;
dataw_pads_out_payload_cmd_o <= 1'd0;
dataw_pads_out_payload_cmd_oe <= 1'd0;
dataw_pads_out_payload_data_o <= 4'd0;
dataw_pads_out_payload_data_oe <= 1'd0;
subfragments_sdphydataw_next_state <= 3'd0;
dataw_accepted1_sdphydataw_next_value0 <= 1'd0;
dataw_sink_ready <= 1'd0;
dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0;
dataw_pads_out_payload_clk <= 1'd0;
dataw_crc_reset <= 1'd0;
dataw_crc_error1_sdphydataw_next_value1 <= 1'd0;
dataw_pads_out_payload_cmd_o <= 1'd0;
dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0;
dataw_stop <= 1'd0;
dataw_pads_out_payload_cmd_oe <= 1'd0;
dataw_write_error1_sdphydataw_next_value2 <= 1'd0;
dataw_pads_out_payload_data_o <= 4'd0;
dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0;
dataw_pads_out_payload_data_oe <= 1'd0;
dataw_count_sdphydataw_next_value3 <= 8'd0;
dataw_count_sdphydataw_next_value_ce3 <= 1'd0;
dataw_sink_ready <= 1'd0;
dataw_stop <= 1'd0;
subfragments_sdphydataw_next_state <= subfragments_sdphydataw_state;
case (subfragments_sdphydataw_state)
1'd1: begin
@ -1670,16 +1678,16 @@ always @(*) begin
datar_source_payload_data <= 8'd0;
datar_source_payload_status <= 3'd0;
datar_stop <= 1'd0;
datar_pads_out_payload_clk <= 1'd0;
subfragments_sdphydatar_next_state <= 3'd0;
datar_count_sdphydatar_next_value0 <= 10'd0;
datar_count_sdphydatar_next_value_ce0 <= 1'd0;
datar_datar_source_source_ready0 <= 1'd0;
datar_timeout_sdphydatar_next_value1 <= 32'd0;
datar_timeout_sdphydatar_next_value_ce1 <= 1'd0;
datar_datar_reset_sdphydatar_next_value2 <= 1'd0;
datar_sink_ready <= 1'd0;
datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0;
datar_pads_out_payload_clk <= 1'd0;
datar_datar_source_source_ready0 <= 1'd0;
datar_sink_ready <= 1'd0;
subfragments_sdphydatar_next_state <= subfragments_sdphydatar_state;
case (subfragments_sdphydatar_state)
1'd1: begin
@ -1906,14 +1914,14 @@ always @(*) begin
end
end
always @(*) begin
subfragments_sdcore_crc16inserter_next_state <= 1'd0;
sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 3'd0;
sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd0;
sdcore_crc16_inserter_sink_ready <= 1'd0;
sdcore_crc16_inserter_source_valid <= 1'd0;
sdcore_crc16_inserter_source_first <= 1'd0;
sdcore_crc16_inserter_source_last <= 1'd0;
sdcore_crc16_inserter_source_payload_data <= 8'd0;
sdcore_crc16_inserter_sink_ready <= 1'd0;
subfragments_sdcore_crc16inserter_next_state <= 1'd0;
sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 3'd0;
sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd0;
subfragments_sdcore_crc16inserter_next_state <= subfragments_sdcore_crc16inserter_state;
case (subfragments_sdcore_crc16inserter_state)
1'd1: begin
@ -2064,47 +2072,47 @@ assign sdcore_fifo_syncfifo_dout = sdcore_fifo_rdport_dat_r;
assign sdcore_fifo_syncfifo_writable = (sdcore_fifo_level != 4'd8);
assign sdcore_fifo_syncfifo_readable = (sdcore_fifo_level != 1'd0);
always @(*) begin
sdcore_cmd_response_status_sdcore_fsm_next_value8 <= 128'd0;
sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd0;
sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0;
sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd0;
sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0;
sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd0;
sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0;
sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd0;
sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0;
sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd0;
cmdr_sink_valid <= 1'd0;
cmdr_sink_payload_cmd_type <= 2'd0;
cmdr_sink_payload_data_type <= 2'd0;
cmdr_sink_payload_length <= 8'd0;
cmdr_source_ready <= 1'd0;
dataw_sink_valid <= 1'd0;
sdcore_cmd_response_status_sdcore_fsm_next_value8 <= 128'd0;
sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd0;
dataw_sink_first <= 1'd0;
dataw_sink_last <= 1'd0;
dataw_sink_payload_data <= 8'd0;
subfragments_sdcore_fsm_next_state <= 3'd0;
cmdw_sink_valid <= 1'd0;
sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0;
sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd0;
datar_sink_valid <= 1'd0;
cmdw_sink_last <= 1'd0;
datar_sink_last <= 1'd0;
cmdw_sink_payload_data <= 8'd0;
datar_sink_payload_block_length <= 10'd0;
cmdw_sink_payload_cmd_type <= 2'd0;
datar_source_ready <= 1'd0;
sdcore_crc16_inserter_source_ready <= 1'd0;
sdcore_sink_sink_valid1 <= 1'd0;
subfragments_sdcore_fsm_next_state <= 3'd0;
sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0;
sdcore_sink_sink_first1 <= 1'd0;
sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd0;
sdcore_sink_sink_last1 <= 1'd0;
sdcore_sink_sink_payload_data1 <= 8'd0;
sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0;
sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd0;
cmdw_sink_payload_data <= 8'd0;
cmdw_sink_payload_cmd_type <= 2'd0;
datar_sink_payload_block_length <= 10'd0;
sdcore_cmd_count_sdcore_fsm_next_value2 <= 3'd0;
datar_source_ready <= 1'd0;
sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd0;
sdcore_crc16_inserter_source_ready <= 1'd0;
sdcore_data_count_sdcore_fsm_next_value3 <= 32'd0;
sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd0;
datar_sink_last <= 1'd0;
sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0;
sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd0;
sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0;
sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd0;
sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0;
sdcore_sink_sink_valid1 <= 1'd0;
sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd0;
sdcore_sink_sink_first1 <= 1'd0;
sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0;
sdcore_sink_sink_last1 <= 1'd0;
sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd0;
sdcore_sink_sink_payload_data1 <= 8'd0;
subfragments_sdcore_fsm_next_state <= subfragments_sdcore_fsm_state;
case (subfragments_sdcore_fsm_state)
1'd1: begin
@ -2255,10 +2263,10 @@ end
assign sdblock2mem_start = (sdblock2mem_sink_sink_valid0 & sdblock2mem_sink_sink_first);
always @(*) begin
sdblock2mem_fifo_sink_last <= 1'd0;
sdblock2mem_fifo_sink_valid <= 1'd0;
sdblock2mem_fifo_sink_first <= 1'd0;
sdblock2mem_sink_sink_ready0 <= 1'd0;
sdblock2mem_fifo_sink_payload_data <= 8'd0;
sdblock2mem_fifo_sink_valid <= 1'd0;
sdblock2mem_fifo_sink_first <= 1'd0;
if ((sdblock2mem_wishbonedmawriter_enable_storage & (sdblock2mem_start | sdblock2mem_connect))) begin
sdblock2mem_fifo_sink_valid <= sdblock2mem_sink_sink_valid0;
sdblock2mem_sink_sink_ready0 <= sdblock2mem_fifo_sink_ready;
@ -2286,11 +2294,13 @@ assign sdblock2mem_fifo_syncfifo_we = sdblock2mem_fifo_sink_valid;
assign sdblock2mem_fifo_fifo_in_first = sdblock2mem_fifo_sink_first;
assign sdblock2mem_fifo_fifo_in_last = sdblock2mem_fifo_sink_last;
assign sdblock2mem_fifo_fifo_in_payload_data = sdblock2mem_fifo_sink_payload_data;
assign sdblock2mem_fifo_source_valid = sdblock2mem_fifo_syncfifo_readable;
assign sdblock2mem_fifo_source_valid = sdblock2mem_fifo_readable;
assign sdblock2mem_fifo_source_first = sdblock2mem_fifo_fifo_out_first;
assign sdblock2mem_fifo_source_last = sdblock2mem_fifo_fifo_out_last;
assign sdblock2mem_fifo_source_payload_data = sdblock2mem_fifo_fifo_out_payload_data;
assign sdblock2mem_fifo_syncfifo_re = sdblock2mem_fifo_source_ready;
assign sdblock2mem_fifo_re = sdblock2mem_fifo_source_ready;
assign sdblock2mem_fifo_syncfifo_re = (sdblock2mem_fifo_syncfifo_readable & ((~sdblock2mem_fifo_readable) | sdblock2mem_fifo_re));
assign sdblock2mem_fifo_level1 = (sdblock2mem_fifo_level0 + sdblock2mem_fifo_readable);
always @(*) begin
sdblock2mem_fifo_wrport_adr <= 9'd0;
if (sdblock2mem_fifo_replace) begin
@ -2304,8 +2314,9 @@ assign sdblock2mem_fifo_wrport_we = (sdblock2mem_fifo_syncfifo_we & (sdblock2mem
assign sdblock2mem_fifo_do_read = (sdblock2mem_fifo_syncfifo_readable & sdblock2mem_fifo_syncfifo_re);
assign sdblock2mem_fifo_rdport_adr = sdblock2mem_fifo_consume;
assign sdblock2mem_fifo_syncfifo_dout = sdblock2mem_fifo_rdport_dat_r;
assign sdblock2mem_fifo_syncfifo_writable = (sdblock2mem_fifo_level != 10'd512);
assign sdblock2mem_fifo_syncfifo_readable = (sdblock2mem_fifo_level != 1'd0);
assign sdblock2mem_fifo_rdport_re = sdblock2mem_fifo_do_read;
assign sdblock2mem_fifo_syncfifo_writable = (sdblock2mem_fifo_level0 != 10'd512);
assign sdblock2mem_fifo_syncfifo_readable = (sdblock2mem_fifo_level0 != 1'd0);
assign sdblock2mem_source_source_valid = sdblock2mem_converter_source_valid;
assign sdblock2mem_converter_source_ready = sdblock2mem_source_source_ready;
assign sdblock2mem_source_source_first = sdblock2mem_converter_source_first;
@ -2326,15 +2337,15 @@ assign sdblock2mem_wishbonedmawriter_length = sdblock2mem_wishbonedmawriter_leng
assign sdblock2mem_wishbonedmawriter_offset_status = sdblock2mem_wishbonedmawriter_offset;
assign sdblock2mem_wishbonedmawriter_reset = (~sdblock2mem_wishbonedmawriter_enable_storage);
always @(*) begin
sdblock2mem_sink_sink_last1 <= 1'd0;
sdblock2mem_sink_sink_payload_address <= 32'd0;
sdblock2mem_sink_sink_payload_data1 <= 32'd0;
subfragments_next_state <= 2'd0;
sdblock2mem_wishbonedmawriter_offset_next_value <= 32'd0;
sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd0;
sdblock2mem_wishbonedmawriter_done_status <= 1'd0;
sdblock2mem_wishbonedmawriter_sink_ready <= 1'd0;
sdblock2mem_sink_sink_valid1 <= 1'd0;
subfragments_next_state <= 2'd0;
sdblock2mem_wishbonedmawriter_offset_next_value <= 32'd0;
sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd0;
sdblock2mem_sink_sink_last1 <= 1'd0;
sdblock2mem_sink_sink_payload_address <= 32'd0;
sdblock2mem_sink_sink_payload_data1 <= 32'd0;
subfragments_next_state <= subfragments_state;
case (subfragments_state)
1'd1: begin
@ -2393,18 +2404,18 @@ assign sdmem2block_dma_length = sdmem2block_dma_length_storage[31:2];
assign sdmem2block_dma_offset_status = sdmem2block_dma_offset;
assign sdmem2block_dma_reset = (~sdmem2block_dma_enable_storage);
always @(*) begin
sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= 32'd0;
sdmem2block_dma_sink_ready <= 1'd0;
sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd0;
interface1_bus_sel <= 4'd0;
interface1_bus_cyc <= 1'd0;
interface1_bus_stb <= 1'd0;
sdmem2block_dma_source_valid <= 1'd0;
interface1_bus_we <= 1'd0;
subfragments_sdmem2blockdma_fsm_next_state <= 1'd0;
sdmem2block_dma_source_last <= 1'd0;
sdmem2block_dma_source_payload_data <= 32'd0;
subfragments_sdmem2blockdma_fsm_next_state <= 1'd0;
sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= 32'd0;
sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd0;
interface1_bus_adr <= 32'd0;
sdmem2block_dma_sink_ready <= 1'd0;
interface1_bus_sel <= 4'd0;
subfragments_sdmem2blockdma_fsm_next_state <= subfragments_sdmem2blockdma_fsm_state;
case (subfragments_sdmem2blockdma_fsm_state)
1'd1: begin
@ -2431,12 +2442,12 @@ always @(*) begin
endcase
end
always @(*) begin
sdmem2block_dma_sink_valid <= 1'd0;
sdmem2block_dma_done_status <= 1'd0;
sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0;
sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0;
sdmem2block_dma_sink_last <= 1'd0;
sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0;
sdmem2block_dma_sink_payload_address <= 32'd0;
sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0;
sdmem2block_dma_done_status <= 1'd0;
sdmem2block_dma_sink_valid <= 1'd0;
subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd0;
subfragments_sdmem2blockdma_resetinserter_next_state <= subfragments_sdmem2blockdma_resetinserter_state;
case (subfragments_sdmem2blockdma_resetinserter_state)
@ -2503,11 +2514,13 @@ assign sdmem2block_fifo_syncfifo_we = sdmem2block_fifo_sink_valid;
assign sdmem2block_fifo_fifo_in_first = sdmem2block_fifo_sink_first;
assign sdmem2block_fifo_fifo_in_last = sdmem2block_fifo_sink_last;
assign sdmem2block_fifo_fifo_in_payload_data = sdmem2block_fifo_sink_payload_data;
assign sdmem2block_fifo_source_valid = sdmem2block_fifo_syncfifo_readable;
assign sdmem2block_fifo_source_valid = sdmem2block_fifo_readable;
assign sdmem2block_fifo_source_first = sdmem2block_fifo_fifo_out_first;
assign sdmem2block_fifo_source_last = sdmem2block_fifo_fifo_out_last;
assign sdmem2block_fifo_source_payload_data = sdmem2block_fifo_fifo_out_payload_data;
assign sdmem2block_fifo_syncfifo_re = sdmem2block_fifo_source_ready;
assign sdmem2block_fifo_re = sdmem2block_fifo_source_ready;
assign sdmem2block_fifo_syncfifo_re = (sdmem2block_fifo_syncfifo_readable & ((~sdmem2block_fifo_readable) | sdmem2block_fifo_re));
assign sdmem2block_fifo_level1 = (sdmem2block_fifo_level0 + sdmem2block_fifo_readable);
always @(*) begin
sdmem2block_fifo_wrport_adr <= 9'd0;
if (sdmem2block_fifo_replace) begin
@ -2521,8 +2534,9 @@ assign sdmem2block_fifo_wrport_we = (sdmem2block_fifo_syncfifo_we & (sdmem2block
assign sdmem2block_fifo_do_read = (sdmem2block_fifo_syncfifo_readable & sdmem2block_fifo_syncfifo_re);
assign sdmem2block_fifo_rdport_adr = sdmem2block_fifo_consume;
assign sdmem2block_fifo_syncfifo_dout = sdmem2block_fifo_rdport_dat_r;
assign sdmem2block_fifo_syncfifo_writable = (sdmem2block_fifo_level != 10'd512);
assign sdmem2block_fifo_syncfifo_readable = (sdmem2block_fifo_level != 1'd0);
assign sdmem2block_fifo_rdport_re = sdmem2block_fifo_do_read;
assign sdmem2block_fifo_syncfifo_writable = (sdmem2block_fifo_level0 != 10'd512);
assign sdmem2block_fifo_syncfifo_readable = (sdmem2block_fifo_level0 != 1'd0);
assign eventmanager_card_detect0 = card_detect_status1;
assign eventmanager_card_detect1 = card_detect_pending;
always @(*) begin
@ -2566,8 +2580,8 @@ always @(*) begin
litesdcardcore_next_state <= 1'd0;
litesdcardcore_litesdcardcore_adr <= 14'd0;
litesdcardcore_litesdcardcore_we <= 1'd0;
litesdcardcore_litesdcardcore_wishbone_ack <= 1'd0;
litesdcardcore_litesdcardcore_dat_w <= 32'd0;
litesdcardcore_litesdcardcore_wishbone_ack <= 1'd0;
litesdcardcore_next_state <= litesdcardcore_state;
case (litesdcardcore_state)
1'd1: begin
@ -2623,9 +2637,9 @@ assign wb_dma_cyc_1 = (litesdcardcore_shared_cyc & litesdcardcore_slave_sel);
assign litesdcardcore_shared_err = wb_dma_err_1;
assign litesdcardcore_wait = ((litesdcardcore_shared_stb & litesdcardcore_shared_cyc) & (~litesdcardcore_shared_ack));
always @(*) begin
litesdcardcore_error <= 1'd0;
litesdcardcore_shared_dat_r <= 32'd0;
litesdcardcore_shared_ack <= 1'd0;
litesdcardcore_error <= 1'd0;
litesdcardcore_shared_ack <= wb_dma_ack_1;
litesdcardcore_shared_dat_r <= ({32{litesdcardcore_slave_sel_r}} & wb_dma_dat_r_1);
if (litesdcardcore_done) begin
@ -2636,7 +2650,7 @@ always @(*) begin
end
assign litesdcardcore_done = (litesdcardcore_count == 1'd0);
assign litesdcardcore_csrbank0_sel = (litesdcardcore_interface0_bank_bus_adr[13:9] == 1'd0);
assign litesdcardcore_csrbank0_reset0_r = litesdcardcore_interface0_bank_bus_dat_w[0];
assign litesdcardcore_csrbank0_reset0_r = litesdcardcore_interface0_bank_bus_dat_w[1:0];
always @(*) begin
litesdcardcore_csrbank0_reset0_re <= 1'd0;
litesdcardcore_csrbank0_reset0_we <= 1'd0;
@ -2663,7 +2677,14 @@ always @(*) begin
litesdcardcore_csrbank0_bus_errors_we <= (~litesdcardcore_interface0_bank_bus_we);
end
end
assign litesdcardcore_csrbank0_reset0_w = reset_storage;
always @(*) begin
soc_rst <= 1'd0;
if (reset_re) begin
soc_rst <= reset_storage[0];
end
end
assign cpu_rst = reset_storage[1];
assign litesdcardcore_csrbank0_reset0_w = reset_storage[1:0];
assign litesdcardcore_csrbank0_scratch0_w = scratch_storage[31:0];
assign litesdcardcore_csrbank0_bus_errors_w = bus_errors_status[31:0];
assign bus_errors_we = litesdcardcore_csrbank0_bus_errors_we;
@ -3016,8 +3037,8 @@ always @(*) begin
end
assign init_initialize_r = litesdcardcore_interface5_bank_bus_dat_w[0];
always @(*) begin
init_initialize_we <= 1'd0;
init_initialize_re <= 1'd0;
init_initialize_we <= 1'd0;
if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 2'd2))) begin
init_initialize_re <= litesdcardcore_interface5_bank_bus_we;
init_initialize_we <= (~litesdcardcore_interface5_bank_bus_we);
@ -3555,6 +3576,13 @@ always @(posedge sys_clk) begin
end
sdblock2mem_done_d <= sdblock2mem_wishbonedmawriter_done_status;
sdblock2mem_irq <= (sdblock2mem_wishbonedmawriter_done_status & (~sdblock2mem_done_d));
if (sdblock2mem_fifo_syncfifo_re) begin
sdblock2mem_fifo_readable <= 1'd1;
end else begin
if (sdblock2mem_fifo_re) begin
sdblock2mem_fifo_readable <= 1'd0;
end
end
if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin
sdblock2mem_fifo_produce <= (sdblock2mem_fifo_produce + 1'd1);
end
@ -3563,11 +3591,11 @@ always @(posedge sys_clk) begin
end
if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin
if ((~sdblock2mem_fifo_do_read)) begin
sdblock2mem_fifo_level <= (sdblock2mem_fifo_level + 1'd1);
sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 + 1'd1);
end
end else begin
if (sdblock2mem_fifo_do_read) begin
sdblock2mem_fifo_level <= (sdblock2mem_fifo_level - 1'd1);
sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 - 1'd1);
end
end
if (sdblock2mem_converter_source_ready) begin
@ -3649,6 +3677,13 @@ always @(posedge sys_clk) begin
sdmem2block_converter_mux <= (sdmem2block_converter_mux + 1'd1);
end
end
if (sdmem2block_fifo_syncfifo_re) begin
sdmem2block_fifo_readable <= 1'd1;
end else begin
if (sdmem2block_fifo_re) begin
sdmem2block_fifo_readable <= 1'd0;
end
end
if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin
sdmem2block_fifo_produce <= (sdmem2block_fifo_produce + 1'd1);
end
@ -3657,11 +3692,11 @@ always @(posedge sys_clk) begin
end
if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin
if ((~sdmem2block_fifo_do_read)) begin
sdmem2block_fifo_level <= (sdmem2block_fifo_level + 1'd1);
sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 + 1'd1);
end
end else begin
if (sdmem2block_fifo_do_read) begin
sdmem2block_fifo_level <= (sdmem2block_fifo_level - 1'd1);
sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 - 1'd1);
end
end
if (card_detect_clear) begin
@ -3722,7 +3757,7 @@ always @(posedge sys_clk) begin
endcase
end
if (litesdcardcore_csrbank0_reset0_re) begin
reset_storage <= litesdcardcore_csrbank0_reset0_r;
reset_storage[1:0] <= litesdcardcore_csrbank0_reset0_r;
end
reset_re <= litesdcardcore_csrbank0_reset0_re;
if (litesdcardcore_csrbank0_scratch0_re) begin
@ -3932,7 +3967,7 @@ always @(posedge sys_clk) begin
clocker_re <= litesdcardcore_csrbank5_clocker_divider0_re;
dataw_re <= litesdcardcore_csrbank5_dataw_status_re;
if (sys_rst) begin
reset_storage <= 1'd0;
reset_storage <= 2'd0;
reset_re <= 1'd0;
scratch_storage <= 32'd305419896;
scratch_re <= 1'd0;
@ -4015,7 +4050,8 @@ always @(posedge sys_clk) begin
sdcore_data_error <= 1'd0;
sdcore_data_timeout <= 1'd0;
sdblock2mem_irq <= 1'd0;
sdblock2mem_fifo_level <= 10'd0;
sdblock2mem_fifo_readable <= 1'd0;
sdblock2mem_fifo_level0 <= 10'd0;
sdblock2mem_fifo_produce <= 9'd0;
sdblock2mem_fifo_consume <= 9'd0;
sdblock2mem_converter_source_payload_data <= 32'd0;
@ -4049,7 +4085,8 @@ always @(posedge sys_clk) begin
sdmem2block_dma_offset_re <= 1'd0;
sdmem2block_dma_offset <= 32'd0;
sdmem2block_converter_mux <= 2'd0;
sdmem2block_fifo_level <= 10'd0;
sdmem2block_fifo_readable <= 1'd0;
sdmem2block_fifo_level0 <= 10'd0;
sdmem2block_fifo_produce <= 9'd0;
sdmem2block_fifo_consume <= 9'd0;
sdmem2block_count <= 9'd0;
@ -4095,6 +4132,7 @@ assign sdcore_fifo_rdport_dat_r = storage[sdcore_fifo_rdport_adr];
reg [9:0] storage_1[0:511];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
always @(posedge sys_clk) begin
if (sdblock2mem_fifo_wrport_we)
storage_1[sdblock2mem_fifo_wrport_adr] <= sdblock2mem_fifo_wrport_dat_w;
@ -4102,24 +4140,29 @@ always @(posedge sys_clk) begin
end
always @(posedge sys_clk) begin
if (sdblock2mem_fifo_rdport_re)
memdat_2 <= storage_1[sdblock2mem_fifo_rdport_adr];
end
assign sdblock2mem_fifo_wrport_dat_r = memdat_1;
assign sdblock2mem_fifo_rdport_dat_r = storage_1[sdblock2mem_fifo_rdport_adr];
assign sdblock2mem_fifo_rdport_dat_r = memdat_2;
reg [9:0] storage_2[0:511];
reg [9:0] memdat_2;
reg [9:0] memdat_3;
reg [9:0] memdat_4;
always @(posedge sys_clk) begin
if (sdmem2block_fifo_wrport_we)
storage_2[sdmem2block_fifo_wrport_adr] <= sdmem2block_fifo_wrport_dat_w;
memdat_2 <= storage_2[sdmem2block_fifo_wrport_adr];
memdat_3 <= storage_2[sdmem2block_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (sdmem2block_fifo_rdport_re)
memdat_4 <= storage_2[sdmem2block_fifo_rdport_adr];
end
assign sdmem2block_fifo_wrport_dat_r = memdat_2;
assign sdmem2block_fifo_rdport_dat_r = storage_2[sdmem2block_fifo_rdport_adr];
assign sdmem2block_fifo_wrport_dat_r = memdat_3;
assign sdmem2block_fifo_rdport_dat_r = memdat_4;
IOBUF IOBUF(
.I(xilinxsdrtristateimpl0__o),

4
litesdcard/litesdcard.core
View File

@ -9,7 +9,7 @@ generators:
description: Generate a litesdcard SD-card controller
usage: |
litesdcard_gen adds the pre-generated LiteX LiteSDCard SD-card controller
based on the board type.
based on the vendor type.
Parameters:
board: The board type (arty)
vendor: The vendor type (xilinx)

11
microwatt.core
View File

@ -228,12 +228,13 @@ targets:
nexys_video:
default_tool: vivado
filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
parameters:
- memory_size
- ram_init_file
- use_litedram=true
- use_liteeth=true
- use_litesdcard=true
- disable_flatten_core
- no_bram
- spi_flash_offset=10485760
@ -241,7 +242,7 @@ targets:
- uart_is_16550
- has_fpu
- has_btc
generate: [litedram_nexys_video, liteeth_nexys_video]
generate: [litedram_nexys_video, liteeth_nexys_video, litesdcard_nexys_video]
tools:
vivado: {part : xc7a200tsbg484-1}
toplevel : toplevel
@ -365,7 +366,11 @@ generate:
litesdcard_arty:
generator: litesdcard_gen
parameters: {board : arty}
parameters: {vendor : xilinx}
litesdcard_nexys_video:
generator: litesdcard_gen
parameters: {vendor : xilinx}
litedram_nexys_video:
generator: litedram_gen