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spr: Add translation from SPR to special GPR number
We will want to store some SPRs in the register file using a set of "extra" registers. This provides a function for doing the translation along with some SPR definitions. This isn't used yet Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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committed by
Paul Mackerras
parent
5a0458dec1
commit
afdd593502
64
common.vhdl
64
common.vhdl
@@ -12,10 +12,31 @@ package common is
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function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
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constant SPR_XER : spr_num_t := 1;
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constant SPR_LR : spr_num_t := 8;
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constant SPR_CTR : spr_num_t := 9;
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constant SPR_TB : spr_num_t := 268;
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constant SPR_XER : spr_num_t := 1;
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constant SPR_LR : spr_num_t := 8;
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constant SPR_CTR : spr_num_t := 9;
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constant SPR_TB : spr_num_t := 268;
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constant SPR_SRR0 : spr_num_t := 26;
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constant SPR_SRR1 : spr_num_t := 27;
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constant SPR_HSRR0 : spr_num_t := 314;
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constant SPR_HSRR1 : spr_num_t := 315;
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constant SPR_SPRG0 : spr_num_t := 272;
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constant SPR_SPRG1 : spr_num_t := 273;
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constant SPR_SPRG2 : spr_num_t := 274;
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constant SPR_SPRG3 : spr_num_t := 275;
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constant SPR_SPRG3U : spr_num_t := 259;
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constant SPR_HSPRG0 : spr_num_t := 304;
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constant SPR_HSPRG1 : spr_num_t := 305;
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-- Some SPRs are stored in the register file, they use the magic
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-- GPR numbers above 31.
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--
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-- The function fast_spr_num() returns the corresponding fast
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-- pseudo-GPR number for a given SPR number. The result MSB
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-- indicates if this is indeed a fast SPR. If clear, then
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-- the SPR is not stored in the GPR file.
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--
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function fast_spr_num(spr: spr_num_t) return std_ulogic_vector;
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-- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
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-- in the CR file as a kind of CR extension (with a separate write
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@@ -282,4 +303,39 @@ package body common is
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begin
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return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
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end;
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function fast_spr_num(spr: spr_num_t) return std_ulogic_vector is
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variable n : integer range 0 to 31;
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begin
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case spr is
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when SPR_LR =>
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n := 0;
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when SPR_CTR =>
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n:= 1;
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when SPR_SRR0 =>
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n := 2;
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when SPR_SRR1 =>
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n := 3;
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when SPR_HSRR0 =>
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n := 4;
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when SPR_HSRR1 =>
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n := 5;
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when SPR_SPRG0 =>
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n := 6;
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when SPR_SPRG1 =>
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n := 7;
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when SPR_SPRG2 =>
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n := 8;
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when SPR_SPRG3 | SPR_SPRG3U =>
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n := 9;
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when SPR_HSPRG0 =>
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n := 10;
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when SPR_HSPRG1 =>
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n := 11;
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when SPR_XER =>
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n := 12;
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when others =>
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return "000000";
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end case;
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return "1" & std_ulogic_vector(to_unsigned(n, 5));
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end;
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end common;
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