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https://github.com/antonblanchard/microwatt.git
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execute1: Implement trace interrupts
Trace interrupts occur when the MSR[TE] field is non-zero and an instruction other than rfid has been successfully completed. A trace interrupt occurs before the next instruction is executed or any asynchronous interrupt is taken. Since the trace interrupt is defined to set SRR1 bits depending on whether the traced instruction is a load or an instruction treated as a load, or a store or an instruction treated as a store, we need to make sure the treated-as-a-load instructions (icbi, icbt, dcbt, dcbst, dcbf) and the treated-as-a-store instructions (dcbtst, dcbz) have the correct opcodes in decode1. Several of them were previously marked as OP_NOP. We don't yet implement the SIAR or SDAR registers, which should be set by trace interrupts. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
@@ -13,6 +13,8 @@ package common is
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constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode
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constant MSR_EE : integer := (63 - 48); -- External interrupt Enable
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constant MSR_PR : integer := (63 - 49); -- PRoblem state
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constant MSR_SE : integer := (63 - 53); -- Single-step bit of TE field
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constant MSR_BE : integer := (63 - 54); -- Branch trace bit of TE field
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constant MSR_IR : integer := (63 - 58); -- Instruction Relocation
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constant MSR_DR : integer := (63 - 59); -- Data Relocation
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constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt
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10
decode1.vhdl
10
decode1.vhdl
@@ -201,10 +201,10 @@ architecture behaviour of decode1 is
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2#1000111010# => (ALU, OP_CNTZ, NONE, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- cnttzd
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2#1000011010# => (ALU, OP_CNTZ, NONE, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- cnttzw
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2#1011110011# => (ALU, OP_DARN, NONE, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- darn
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2#0001010110# => (ALU, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbf
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2#0000110110# => (ALU, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbst
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2#0100010110# => (ALU, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbt
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2#0011110110# => (ALU, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbtst
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2#0001010110# => (ALU, OP_DCBF, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbf
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2#0000110110# => (ALU, OP_DCBST, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbst
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2#0100010110# => (ALU, OP_DCBT, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbt
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2#0011110110# => (ALU, OP_DCBTST, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- dcbtst
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2#1111110110# => (LDST, OP_DCBZ, RA_OR_ZERO, RB, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- dcbz
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2#0110001001# => (ALU, OP_DIVE, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- divdeu
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2#1110001001# => (ALU, OP_DIVE, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- divdeuo
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@@ -230,7 +230,7 @@ architecture behaviour of decode1 is
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2#1101111010# => (ALU, OP_EXTSWSLI, NONE, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- extswsli
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2#1101111011# => (ALU, OP_EXTSWSLI, NONE, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- extswsli
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2#1111010110# => (ALU, OP_ICBI, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- icbi
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2#0000010110# => (ALU, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- icbt
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2#0000010110# => (ALU, OP_ICBT, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- icbt
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2#0000001111# => (ALU, OP_ISEL, RA_OR_ZERO, RB, NONE, RT, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- isel
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2#0000101111# => (ALU, OP_ISEL, RA_OR_ZERO, RB, NONE, RT, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- isel
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2#0001001111# => (ALU, OP_ISEL, RA_OR_ZERO, RB, NONE, RT, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- isel
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@@ -53,6 +53,8 @@ architecture behaviour of execute1 is
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f : Execute1ToFetch1Type;
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busy: std_ulogic;
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terminate: std_ulogic;
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trace_next : std_ulogic;
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prev_op : insn_type_t;
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lr_update : std_ulogic;
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next_lr : std_ulogic_vector(63 downto 0);
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mul_in_progress : std_ulogic;
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@@ -69,7 +71,7 @@ architecture behaviour of execute1 is
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end record;
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constant reg_type_init : reg_type :=
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(e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
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busy => '0', lr_update => '0', terminate => '0',
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busy => '0', lr_update => '0', terminate => '0', trace_next => '0', prev_op => OP_ILLEGAL,
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mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
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slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
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next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
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@@ -330,6 +332,7 @@ begin
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variable abs_branch : std_ulogic;
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variable spr_val : std_ulogic_vector(63 downto 0);
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variable addend : std_ulogic_vector(127 downto 0);
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variable do_trace : std_ulogic;
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begin
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result := (others => '0');
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sum_with_carry := (others => '0');
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@@ -525,6 +528,11 @@ begin
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v.e.mode_32bit := not ctrl.msr(MSR_SF);
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do_trace := valid_in and ctrl.msr(MSR_SE);
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if valid_in = '1' then
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v.prev_op := e_in.insn_type;
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end if;
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if ctrl.irq_state = WRITE_SRR1 then
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v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
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v.e.exc_write_data := ctrl.srr1;
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@@ -532,13 +540,29 @@ begin
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ctrl_tmp.msr(MSR_SF) <= '1';
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ctrl_tmp.msr(MSR_EE) <= '0';
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ctrl_tmp.msr(MSR_PR) <= '0';
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ctrl_tmp.msr(MSR_SE) <= '0';
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ctrl_tmp.msr(MSR_BE) <= '0';
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ctrl_tmp.msr(MSR_IR) <= '0';
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ctrl_tmp.msr(MSR_DR) <= '0';
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ctrl_tmp.msr(MSR_RI) <= '0';
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ctrl_tmp.msr(MSR_LE) <= '1';
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v.e.valid := '1';
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v.trace_next := '0';
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report "Writing SRR1: " & to_hstring(ctrl.srr1);
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elsif r.trace_next = '1' and valid_in = '1' then
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-- Generate a trace interrupt rather than executing the next instruction
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-- or taking any asynchronous interrupt
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v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
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ctrl_tmp.srr1(63 - 33) <= '1';
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if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
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r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
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ctrl_tmp.srr1(63 - 35) <= '1';
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elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
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ctrl_tmp.srr1(63 - 36) <= '1';
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end if;
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exception := '1';
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elsif irq_valid = '1' and valid_in = '1' then
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-- we need two cycles to write srr0 and 1
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-- will need more when we have to write HEIR
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@@ -594,7 +618,7 @@ begin
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else
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illegal := '1';
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end if;
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when OP_NOP =>
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when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
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-- Do nothing
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when OP_ADD | OP_CMP | OP_TRAP =>
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result := sum_with_carry(63 downto 0);
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@@ -715,6 +739,9 @@ begin
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is_branch := '1';
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taken_branch := '1';
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abs_branch := insn_aa(e_in.insn);
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if ctrl.msr(MSR_BE) = '1' then
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do_trace := '1';
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end if;
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when OP_BC =>
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-- read_data1 is CTR
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bo := insn_bo(e_in.insn);
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@@ -727,6 +754,9 @@ begin
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is_branch := '1';
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taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
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abs_branch := insn_aa(e_in.insn);
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if ctrl.msr(MSR_BE) = '1' then
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do_trace := '1';
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end if;
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when OP_BCREG =>
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-- read_data1 is CTR
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-- read_data2 is target register (CTR, LR or TAR)
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@@ -740,6 +770,9 @@ begin
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is_branch := '1';
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taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
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abs_branch := '1';
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if ctrl.msr(MSR_BE) = '1' then
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do_trace := '1';
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end if;
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when OP_RFID =>
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v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
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@@ -760,6 +793,7 @@ begin
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is_branch := '1';
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taken_branch := '1';
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abs_branch := '1';
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do_trace := '0';
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when OP_CNTZ =>
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v.e.valid := '0';
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@@ -1135,6 +1169,10 @@ begin
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end if;
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end if;
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if do_trace = '1' then
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v.trace_next := '1';
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end if;
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v.e.write_data := result;
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v.e.write_enable := result_en and not exception;
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