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litedram: Update to new LiteX/LiteDRAM version

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Things have changed a bit in upstream LiteX. LiteDRAM now exposes a
wishbone for the CSRs for example.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2020-05-12 20:27:15 +10:00
parent 13e84b0bbb
commit c19b5b8cc7
20 changed files with 7250 additions and 6131 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
fpga/top-arty.vhdl
View File

@@ -68,7 +68,7 @@ architecture behaviour of toplevel is
-- DRAM wishbone connection
signal wb_dram_in : wishbone_master_out;
signal wb_dram_out : wishbone_slave_out;
signal wb_dram_csr : std_ulogic;
signal wb_dram_ctrl : std_ulogic;
signal wb_dram_init : std_ulogic;
-- Control/status
@@ -104,7 +104,7 @@ begin
uart0_rxd => uart_main_rx,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_dram_csr => wb_dram_csr,
wb_dram_ctrl => wb_dram_ctrl,
wb_dram_init => wb_dram_init,
alt_reset => core_alt_reset
);
@@ -194,7 +194,7 @@ begin
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_is_csr => wb_dram_csr,
wb_is_ctrl => wb_dram_ctrl,
wb_is_init => wb_dram_init,
serial_tx => uart_pmod_tx,

6
fpga/top-nexys-video.vhdl
View File

@@ -60,7 +60,7 @@ architecture behaviour of toplevel is
-- DRAM wishbone connection
signal wb_dram_in : wishbone_master_out;
signal wb_dram_out : wishbone_slave_out;
signal wb_dram_csr : std_ulogic;
signal wb_dram_ctrl : std_ulogic;
signal wb_dram_init : std_ulogic;
-- Control/status
@@ -87,7 +87,7 @@ begin
uart0_rxd => uart_main_rx,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_dram_csr => wb_dram_csr,
wb_dram_ctrl => wb_dram_ctrl,
wb_dram_init => wb_dram_init,
alt_reset => core_alt_reset
);
@@ -175,7 +175,7 @@ begin
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_is_csr => wb_dram_csr,
wb_is_ctrl => wb_dram_ctrl,
wb_is_init => wb_dram_init,
serial_tx => open,

3
include/console.h
View File

@@ -6,4 +6,7 @@ void potato_uart_irq_dis(void);
int getchar(void);
int putchar(int c);
int puts(const char *str);
#ifndef __USE_LIBC
size_t strlen(const char *s);
#endif

3
include/microwatt_soc.h
View File

@@ -31,4 +31,7 @@
#define POTATO_CONSOLE_CLOCK_DIV 0x18
#define POTATO_CONSOLE_IRQ_EN 0x20
/* Definition for the LiteDRAM control registers */
#define DRAM_CTRL_BASE 0xc0100000
#endif /* __MICROWATT_SOC_H */

2
lib/console.c
View File

@@ -120,6 +120,7 @@ int puts(const char *str)
return 0;
}
#ifndef __USE_LIBC
size_t strlen(const char *s)
{
size_t len = 0;
@@ -129,3 +130,4 @@ size_t strlen(const char *s)
return len;
}
#endif

4
litedram/gen-src/arty.yml
View File

@@ -37,7 +37,5 @@
},
# CSR Port -----------------------------------------------------------------
"csr_expose": "False", # expose access to CSR (I/O) ports
"csr_align" : 32, # CSR alignment
"csr_base" : 0xc0100000 # For cpu=None only
"csr_base" : 0xc0100000, # For cpu=None only
}

3
litedram/gen-src/generate.py
View File

@@ -104,8 +104,7 @@ def generate_one(t, mw_init):
# Override values for mw_init
if mw_init:
core_config["cpu"] = None
core_config["csr_expose"] = True
core_config["csr_align"] = 64
core_config["csr_alignment"] = 64
# Generate core
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:

3
litedram/gen-src/nexys-video.yml
View File

@@ -37,6 +37,5 @@
},
# CSR Port -----------------------------------------------------------------
"csr_expose": "False", # expose access to CSR (I/O) ports
"csr_align" : 32, # 64-bit alignment
"csr_base" : 0xc0100000, # For cpu=None only
}

4
litedram/gen-src/sdram_init/Makefile
View File

@@ -21,7 +21,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
#### Flags
CPPFLAGS = -nostdinc
CPPFLAGS = -nostdinc -D__USE_LIBC
CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include
CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include)
CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks
@@ -36,7 +36,7 @@ define Q
endef
else
define Q
@echo " [$1] $(3)"
@echo " [$1] " $(shell basename $3)
@$(2)
endef
endif

30
litedram/gen-src/sdram_init/include/system.h
View File

@@ -1,9 +1,18 @@
static inline void flush_cpu_dcache(void) { }
#ifndef __SYSTEM_H
#define __SYSTEM_H
#include "microwatt_soc.h"
#include "io.h"
#define CSR_ACCESSORS_DEFINED
#define CSR_BASE DRAM_CTRL_BASE
#define CONFIG_CPU_NOP "nop"
extern void flush_cpu_dcache(void);
extern void flush_cpu_icache(void);
static inline void flush_l2_cache(void) { }
#define CONFIG_CPU_NOP "nop"
#define CONFIG_CLOCK_FREQUENCY 100000000
/* Fake timer stuff. LiteX should abstract this */
static inline void timer0_en_write(int e) { }
static inline void timer0_reload_write(int r) { }
static inline void timer0_load_write(int l) { }
@@ -15,3 +24,16 @@ static inline uint64_t timer0_value_read(void)
__asm__ volatile ("mfdec %0" : "=r" (val));
return val;
}
static inline void csr_write_simple(unsigned long v, unsigned long a)
{
return writel(v, a);
}
static inline unsigned long csr_read_simple(unsigned long a)
{
return readl(a);
}
#endif /* __SYSTEM_H */

105
litedram/gen-src/sdram_init/main.c
View File

@@ -10,89 +10,7 @@
#include "microwatt_soc.h"
#include "io.h"
#include "sdram.h"
/*
* Core UART functions to implement for a port
*/
static uint64_t potato_uart_base;
#define PROC_FREQ 100000000
#define UART_FREQ 115200
static uint8_t potato_uart_reg_read(int offset)
{
return readb(potato_uart_base + offset);
}
static void potato_uart_reg_write(int offset, uint8_t val)
{
writeb(val, potato_uart_base + offset);
}
static bool potato_uart_rx_empty(void)
{
uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS);
return (val & POTATO_CONSOLE_STATUS_RX_EMPTY) != 0;
}
static int potato_uart_tx_full(void)
{
uint8_t val = potato_uart_reg_read(POTATO_CONSOLE_STATUS);
return (val & POTATO_CONSOLE_STATUS_TX_FULL) != 0;
}
static char potato_uart_read(void)
{
return potato_uart_reg_read(POTATO_CONSOLE_RX);
}
static void potato_uart_write(char c)
{
potato_uart_reg_write(POTATO_CONSOLE_TX, c);
}
static unsigned long potato_uart_divisor(unsigned long proc_freq,
unsigned long uart_freq)
{
return proc_freq / (uart_freq * 16) - 1;
}
void potato_uart_init(void)
{
potato_uart_base = UART_BASE;
potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV,
potato_uart_divisor(PROC_FREQ, UART_FREQ));
}
int getchar(void)
{
while (potato_uart_rx_empty())
/* Do nothing */ ;
return potato_uart_read();
}
int putchar(int c)
{
while (potato_uart_tx_full())
/* Do Nothing */;
potato_uart_write(c);
return c;
}
void putstr(const char *str, unsigned long len)
{
for (unsigned long i = 0; i < len; i++) {
if (str[i] == '\n')
putchar('\r');
putchar(str[i]);
}
}
#include "console.h"
int _printf(const char *fmt, ...)
{
@@ -103,26 +21,33 @@ int _printf(const char *fmt, ...)
va_start(ap, fmt);
count = vsnprintf(buffer, sizeof(buffer), fmt, ap);
va_end(ap);
putstr(buffer, count);
puts(buffer);
return count;
}
void flush_cpu_dcache(void) { }
void flush_cpu_icache(void) { }
void flush_l2_cache(void) { }
void flush_cpu_dcache(void)
{
}
void flush_cpu_icache(void)
{
__asm__ volatile ("icbi 0,0; isync" : : : "memory");
}
void main(void)
{
unsigned long long ftr, val;
int i;
/* Init the UART */
potato_uart_init();
/*
* Let things settle ... not sure why but the UART is
* not happy otherwise. The PLL might need to settle ?
*/
potato_uart_init();
for (i = 0; i < 100000; i++)
potato_uart_reg_read(POTATO_CONSOLE_STATUS);
for (i = 0; i < 10000; i++)
readb(UART_BASE + POTATO_CONSOLE_STATUS);
printf("\n\nWelcome to Microwatt !\n\n");
/* TODO: Add core version information somewhere in syscon, possibly

119
litedram/gen-src/wrapper-mw-init.vhdl
View File

@@ -25,7 +25,7 @@ entity litedram_wrapper is
-- Wishbone ports:
wb_in : in wishbone_master_out;
wb_out : out wishbone_slave_out;
wb_is_csr : in std_ulogic;
wb_is_ctrl : in std_ulogic;
wb_is_init : in std_ulogic;
-- Init core serial debug
@@ -58,32 +58,39 @@ end entity litedram_wrapper;
architecture behaviour of litedram_wrapper is
component litedram_core port (
clk : in std_ulogic;
rst : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
csr_port0_adr : in std_ulogic_vector(13 downto 0);
csr_port0_we : in std_ulogic;
csr_port0_dat_w : in std_ulogic_vector(31 downto 0);
csr_port0_dat_r : out std_ulogic_vector(31 downto 0);
clk : in std_ulogic;
rst : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
wb_ctrl_cyc : in std_ulogic;
wb_ctrl_stb : in std_ulogic;
wb_ctrl_ack : out std_ulogic;
wb_ctrl_we : in std_ulogic;
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
wb_ctrl_err : out std_ulogic;
user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic;
@@ -114,18 +121,19 @@ architecture behaviour of litedram_wrapper is
signal dram_user_reset : std_ulogic;
signal csr_port0_adr : std_ulogic_vector(13 downto 0);
signal csr_port0_we : std_ulogic;
signal csr_port0_dat_w : std_ulogic_vector(31 downto 0);
signal csr_port0_dat_r : std_ulogic_vector(31 downto 0);
signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
signal csr_valid : std_ulogic;
signal csr_write_valid : std_ulogic;
signal wb_ctrl_adr : std_ulogic_vector(29 downto 0);
signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0);
signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0);
signal wb_ctrl_sel : std_ulogic_vector(3 downto 0);
signal wb_ctrl_cyc : std_ulogic;
signal wb_ctrl_stb : std_ulogic;
signal wb_ctrl_ack : std_ulogic;
signal wb_ctrl_we : std_ulogic;
signal wb_init_in : wishbone_master_out;
signal wb_init_out : wishbone_slave_out;
type state_t is (CMD, MWRITE, MREAD, CSR);
type state_t is (CMD, MWRITE, MREAD);
signal state : state_t;
constant INIT_RAM_SIZE : integer := 16384;
@@ -192,7 +200,7 @@ begin
ad3 <= wb_in.adr(3);
-- DRAM data interface signals
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init)
when state = CMD else '0';
user_port0_cmd_we <= wb_in.we when state = CMD else '0';
user_port0_wdata_valid <= '1' when state = MWRITE else '0';
@@ -202,21 +210,21 @@ begin
user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
"00000000" & wb_in.sel;
-- DRAM CSR interface signals. We only support access to the bottom byte
csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
csr_write_valid <= wb_in.we and wb_in.sel(0);
csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0');
csr_port0_dat_w <= wb_in.dat(31 downto 0);
csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
-- DRAM ctrl interface signals
wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2);
wb_ctrl_dat_w <= wb_in.dat(31 downto 0);
wb_ctrl_sel <= wb_in.sel(3 downto 0);
wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl;
wb_ctrl_stb <= wb_in.stb and wb_is_ctrl;
wb_ctrl_we <= wb_in.we;
-- Wishbone out signals
wb_out.ack <= '1' when state = CSR else
wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else
wb_init_out.ack when wb_is_init = '1' else
user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0';
csr_port_read_comb <= x"00000000" & csr_port0_dat_r;
wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else
wb_init_out.dat when wb_is_init = '1' else
user_port0_rdata_data(127 downto 64) when ad3 = '1' else
user_port0_rdata_data(63 downto 0);
@@ -239,9 +247,7 @@ begin
else
case state is
when CMD =>
if csr_valid = '1' then
state <= CSR;
elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
state <= MWRITE when wb_in.we = '1' else MREAD;
end if;
when MWRITE =>
@@ -252,8 +258,6 @@ begin
if user_port0_rdata_valid = '1' then
state <= CMD;
end if;
when CSR =>
state <= CMD;
end case;
end if;
end if;
@@ -283,10 +287,17 @@ begin
init_error => init_error,
user_clk => system_clk,
user_rst => dram_user_reset,
csr_port0_adr => csr_port0_adr,
csr_port0_we => csr_port0_we,
csr_port0_dat_w => csr_port0_dat_w,
csr_port0_dat_r => csr_port0_dat_r,
wb_ctrl_adr => wb_ctrl_adr,
wb_ctrl_dat_w => wb_ctrl_dat_w,
wb_ctrl_dat_r => wb_ctrl_dat_r,
wb_ctrl_sel => wb_ctrl_sel,
wb_ctrl_cyc => wb_ctrl_cyc,
wb_ctrl_stb => wb_ctrl_stb,
wb_ctrl_ack => wb_ctrl_ack,
wb_ctrl_we => wb_ctrl_we,
wb_ctrl_cti => "000",
wb_ctrl_bte => "00",
wb_ctrl_err => open,
user_port_native_0_cmd_valid => user_port0_cmd_valid,
user_port_native_0_cmd_ready => user_port0_cmd_ready,
user_port_native_0_cmd_we => user_port0_cmd_we,

8
litedram/gen-src/wrapper-self-init.vhdl
View File

@@ -25,7 +25,7 @@ entity litedram_wrapper is
-- Wishbone ports:
wb_in : in wishbone_master_out;
wb_out : out wishbone_slave_out;
wb_is_csr : in std_ulogic;
wb_is_ctrl : in std_ulogic;
wb_is_init : in std_ulogic;
-- Init core serial debug
@@ -123,7 +123,7 @@ begin
ad3 <= wb_in.adr(3);
-- DRAM interface signals
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init)
when state = CMD else '0';
user_port0_cmd_we <= wb_in.we when state = CMD else '0';
user_port0_wdata_valid <= '1' when state = MWRITE else '0';
@@ -134,10 +134,10 @@ begin
"00000000" & wb_in.sel;
-- Wishbone out signals. CSR and init memory do nothing, just ack
wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else
wb_out.ack <= '1' when (wb_is_ctrl = '1' or wb_is_init = '1') else
user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0';
wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else
wb_out.dat <= (others => '0') when (wb_is_ctrl = '1' or wb_is_init = '1') else
user_port0_rdata_data(127 downto 64) when ad3 = '1' else
user_port0_rdata_data(63 downto 0);
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;

130
litedram/generated/arty/litedram-wrapper.vhdl
View File

@@ -25,7 +25,7 @@ entity litedram_wrapper is
-- Wishbone ports:
wb_in : in wishbone_master_out;
wb_out : out wishbone_slave_out;
wb_is_csr : in std_ulogic;
wb_is_ctrl : in std_ulogic;
wb_is_init : in std_ulogic;
-- Init core serial debug
@@ -58,32 +58,39 @@ end entity litedram_wrapper;
architecture behaviour of litedram_wrapper is
component litedram_core port (
clk : in std_ulogic;
rst : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
csr_port0_adr : in std_ulogic_vector(13 downto 0);
csr_port0_we : in std_ulogic;
csr_port0_dat_w : in std_ulogic_vector(31 downto 0);
csr_port0_dat_r : out std_ulogic_vector(31 downto 0);
clk : in std_ulogic;
rst : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
wb_ctrl_cyc : in std_ulogic;
wb_ctrl_stb : in std_ulogic;
wb_ctrl_ack : out std_ulogic;
wb_ctrl_we : in std_ulogic;
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
wb_ctrl_err : out std_ulogic;
user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic;
@@ -112,20 +119,19 @@ architecture behaviour of litedram_wrapper is
signal ad3 : std_ulogic;
signal dram_user_reset : std_ulogic;
signal csr_port0_adr : std_ulogic_vector(13 downto 0);
signal csr_port0_we : std_ulogic;
signal csr_port0_dat_w : std_ulogic_vector(31 downto 0);
signal csr_port0_dat_r : std_ulogic_vector(31 downto 0);
signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
signal csr_valid : std_ulogic;
signal csr_write_valid : std_ulogic;
signal wb_ctrl_adr : std_ulogic_vector(29 downto 0);
signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0);
signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0);
signal wb_ctrl_sel : std_ulogic_vector(3 downto 0);
signal wb_ctrl_cyc : std_ulogic;
signal wb_ctrl_stb : std_ulogic;
signal wb_ctrl_ack : std_ulogic;
signal wb_ctrl_we : std_ulogic;
signal wb_init_in : wishbone_master_out;
signal wb_init_out : wishbone_slave_out;
type state_t is (CMD, MWRITE, MREAD, CSR);
type state_t is (CMD, MWRITE, MREAD);
signal state : state_t;
constant INIT_RAM_SIZE : integer := 16384;
@@ -192,7 +198,7 @@ begin
ad3 <= wb_in.adr(3);
-- DRAM data interface signals
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init)
when state = CMD else '0';
user_port0_cmd_we <= wb_in.we when state = CMD else '0';
user_port0_wdata_valid <= '1' when state = MWRITE else '0';
@@ -202,31 +208,28 @@ begin
user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
"00000000" & wb_in.sel;
-- DRAM CSR interface signals. We only support access to the bottom byte
csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
csr_write_valid <= wb_in.we and wb_in.sel(0);
csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0');
csr_port0_dat_w <= wb_in.dat(31 downto 0);
csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
-- DRAM ctrl interface signals
wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2);
wb_ctrl_dat_w <= wb_in.dat(31 downto 0);
wb_ctrl_sel <= wb_in.sel(3 downto 0);
wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl;
wb_ctrl_stb <= wb_in.stb and wb_is_ctrl;
wb_ctrl_we <= wb_in.we;
-- Wishbone out signals
wb_out.ack <= '1' when state = CSR else
wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else
wb_init_out.ack when wb_is_init = '1' else
user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0';
csr_port_read_comb <= x"00000000" & csr_port0_dat_r;
wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else
wb_init_out.dat when wb_is_init = '1' else
user_port0_rdata_data(127 downto 64) when ad3 = '1' else
user_port0_rdata_data(63 downto 0);
-- We don't do pipelining yet.
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
-- Reset ignored, the reset controller use the pll lock signal,
-- and alternate core reset address set when DRAM is not initialized.
--
system_reset <= '0';
-- Use alternate core reset address set when DRAM is not initialized.
core_alt_reset <= not init_done;
-- State machine
@@ -234,14 +237,12 @@ begin
begin
if rising_edge(system_clk) then
if dram_user_reset = '1' then
if system_reset = '1' then
state <= CMD;
else
case state is
when CMD =>
if csr_valid = '1' then
state <= CSR;
elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
state <= MWRITE when wb_in.we = '1' else MREAD;
end if;
when MWRITE =>
@@ -252,8 +253,6 @@ begin
if user_port0_rdata_valid = '1' then
state <= CMD;
end if;
when CSR =>
state <= CMD;
end case;
end if;
end if;
@@ -282,11 +281,18 @@ begin
init_done => init_done,
init_error => init_error,
user_clk => system_clk,
user_rst => dram_user_reset,
csr_port0_adr => csr_port0_adr,
csr_port0_we => csr_port0_we,
csr_port0_dat_w => csr_port0_dat_w,
csr_port0_dat_r => csr_port0_dat_r,
user_rst => system_reset,
wb_ctrl_adr => wb_ctrl_adr,
wb_ctrl_dat_w => wb_ctrl_dat_w,
wb_ctrl_dat_r => wb_ctrl_dat_r,
wb_ctrl_sel => wb_ctrl_sel,
wb_ctrl_cyc => wb_ctrl_cyc,
wb_ctrl_stb => wb_ctrl_stb,
wb_ctrl_ack => wb_ctrl_ack,
wb_ctrl_we => wb_ctrl_we,
wb_ctrl_cti => "000",
wb_ctrl_bte => "00",
wb_ctrl_err => open,
user_port_native_0_cmd_valid => user_port0_cmd_valid,
user_port_native_0_cmd_ready => user_port0_cmd_ready,
user_port_native_0_cmd_we => user_port0_cmd_we,

1547
litedram/generated/arty/litedram_core.init
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3317
litedram/generated/arty/litedram_core.v
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130
litedram/generated/nexys-video/litedram-wrapper.vhdl
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@@ -25,7 +25,7 @@ entity litedram_wrapper is
-- Wishbone ports:
wb_in : in wishbone_master_out;
wb_out : out wishbone_slave_out;
wb_is_csr : in std_ulogic;
wb_is_ctrl : in std_ulogic;
wb_is_init : in std_ulogic;
-- Init core serial debug
@@ -58,32 +58,39 @@ end entity litedram_wrapper;
architecture behaviour of litedram_wrapper is
component litedram_core port (
clk : in std_ulogic;
rst : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
csr_port0_adr : in std_ulogic_vector(13 downto 0);
csr_port0_we : in std_ulogic;
csr_port0_dat_w : in std_ulogic_vector(31 downto 0);
csr_port0_dat_r : out std_ulogic_vector(31 downto 0);
clk : in std_ulogic;
rst : in std_ulogic;
pll_locked : out std_ulogic;
ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
ddram_ba : out std_ulogic_vector(2 downto 0);
ddram_ras_n : out std_ulogic;
ddram_cas_n : out std_ulogic;
ddram_we_n : out std_ulogic;
ddram_cs_n : out std_ulogic;
ddram_dm : out std_ulogic_vector(1 downto 0);
ddram_dq : inout std_ulogic_vector(15 downto 0);
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
ddram_clk_p : out std_ulogic;
ddram_clk_n : out std_ulogic;
ddram_cke : out std_ulogic;
ddram_odt : out std_ulogic;
ddram_reset_n : out std_ulogic;
init_done : out std_ulogic;
init_error : out std_ulogic;
user_clk : out std_ulogic;
user_rst : out std_ulogic;
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
wb_ctrl_cyc : in std_ulogic;
wb_ctrl_stb : in std_ulogic;
wb_ctrl_ack : out std_ulogic;
wb_ctrl_we : in std_ulogic;
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
wb_ctrl_err : out std_ulogic;
user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic;
@@ -112,20 +119,19 @@ architecture behaviour of litedram_wrapper is
signal ad3 : std_ulogic;
signal dram_user_reset : std_ulogic;
signal csr_port0_adr : std_ulogic_vector(13 downto 0);
signal csr_port0_we : std_ulogic;
signal csr_port0_dat_w : std_ulogic_vector(31 downto 0);
signal csr_port0_dat_r : std_ulogic_vector(31 downto 0);
signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
signal csr_valid : std_ulogic;
signal csr_write_valid : std_ulogic;
signal wb_ctrl_adr : std_ulogic_vector(29 downto 0);
signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0);
signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0);
signal wb_ctrl_sel : std_ulogic_vector(3 downto 0);
signal wb_ctrl_cyc : std_ulogic;
signal wb_ctrl_stb : std_ulogic;
signal wb_ctrl_ack : std_ulogic;
signal wb_ctrl_we : std_ulogic;
signal wb_init_in : wishbone_master_out;
signal wb_init_out : wishbone_slave_out;
type state_t is (CMD, MWRITE, MREAD, CSR);
type state_t is (CMD, MWRITE, MREAD);
signal state : state_t;
constant INIT_RAM_SIZE : integer := 16384;
@@ -192,7 +198,7 @@ begin
ad3 <= wb_in.adr(3);
-- DRAM data interface signals
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_ctrl and not wb_is_init)
when state = CMD else '0';
user_port0_cmd_we <= wb_in.we when state = CMD else '0';
user_port0_wdata_valid <= '1' when state = MWRITE else '0';
@@ -202,31 +208,28 @@ begin
user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
"00000000" & wb_in.sel;
-- DRAM CSR interface signals. We only support access to the bottom byte
csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
csr_write_valid <= wb_in.we and wb_in.sel(0);
csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0');
csr_port0_dat_w <= wb_in.dat(31 downto 0);
csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
-- DRAM ctrl interface signals
wb_ctrl_adr <= x"0000" & wb_in.adr(15 downto 2);
wb_ctrl_dat_w <= wb_in.dat(31 downto 0);
wb_ctrl_sel <= wb_in.sel(3 downto 0);
wb_ctrl_cyc <= wb_in.cyc and wb_is_ctrl;
wb_ctrl_stb <= wb_in.stb and wb_is_ctrl;
wb_ctrl_we <= wb_in.we;
-- Wishbone out signals
wb_out.ack <= '1' when state = CSR else
wb_out.ack <= wb_ctrl_ack when wb_is_ctrl ='1' else
wb_init_out.ack when wb_is_init = '1' else
user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0';
csr_port_read_comb <= x"00000000" & csr_port0_dat_r;
wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
wb_out.dat <= (x"00000000" & wb_ctrl_dat_r) when wb_is_ctrl = '1' else
wb_init_out.dat when wb_is_init = '1' else
user_port0_rdata_data(127 downto 64) when ad3 = '1' else
user_port0_rdata_data(63 downto 0);
-- We don't do pipelining yet.
wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
-- Reset ignored, the reset controller use the pll lock signal,
-- and alternate core reset address set when DRAM is not initialized.
--
system_reset <= '0';
-- Use alternate core reset address set when DRAM is not initialized.
core_alt_reset <= not init_done;
-- State machine
@@ -234,14 +237,12 @@ begin
begin
if rising_edge(system_clk) then
if dram_user_reset = '1' then
if system_reset = '1' then
state <= CMD;
else
case state is
when CMD =>
if csr_valid = '1' then
state <= CSR;
elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
state <= MWRITE when wb_in.we = '1' else MREAD;
end if;
when MWRITE =>
@@ -252,8 +253,6 @@ begin
if user_port0_rdata_valid = '1' then
state <= CMD;
end if;
when CSR =>
state <= CMD;
end case;
end if;
end if;
@@ -282,11 +281,18 @@ begin
init_done => init_done,
init_error => init_error,
user_clk => system_clk,
user_rst => dram_user_reset,
csr_port0_adr => csr_port0_adr,
csr_port0_we => csr_port0_we,
csr_port0_dat_w => csr_port0_dat_w,
csr_port0_dat_r => csr_port0_dat_r,
user_rst => system_reset,
wb_ctrl_adr => wb_ctrl_adr,
wb_ctrl_dat_w => wb_ctrl_dat_w,
wb_ctrl_dat_r => wb_ctrl_dat_r,
wb_ctrl_sel => wb_ctrl_sel,
wb_ctrl_cyc => wb_ctrl_cyc,
wb_ctrl_stb => wb_ctrl_stb,
wb_ctrl_ack => wb_ctrl_ack,
wb_ctrl_we => wb_ctrl_we,
wb_ctrl_cti => "000",
wb_ctrl_bte => "00",
wb_ctrl_err => open,
user_port_native_0_cmd_valid => user_port0_cmd_valid,
user_port_native_0_cmd_ready => user_port0_cmd_ready,
user_port_native_0_cmd_we => user_port0_cmd_we,

920
litedram/generated/nexys-video/litedram_core.init
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7027
litedram/generated/nexys-video/litedram_core.v
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File diff suppressed because it is too large Load Diff

14
soc.vhdl
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@@ -17,7 +17,7 @@ use work.wishbone_types.all;
-- 0xc0000000: SYSCON
-- 0xc0002000: UART0
-- 0xc0004000: XICS ICP
-- 0xc0100000: DRAM CSRs
-- 0xc0100000: LiteDRAM control (CSRs)
-- 0xf0000000: Block RAM (aliased & repeated)
-- 0xffff0000: DRAM init code (if any)
@@ -39,7 +39,7 @@ entity soc is
-- DRAM controller signals
wb_dram_in : out wishbone_master_out;
wb_dram_out : in wishbone_slave_out;
wb_dram_csr : out std_ulogic;
wb_dram_ctrl : out std_ulogic;
wb_dram_init : out std_ulogic;
-- UART0 signals:
@@ -162,7 +162,7 @@ begin
SLAVE_BRAM,
SLAVE_DRAM,
SLAVE_DRAM_INIT,
SLAVE_DRAM_CSR,
SLAVE_DRAM_CTRL,
SLAVE_ICP_0,
SLAVE_NONE);
variable slave : slave_type;
@@ -185,7 +185,7 @@ begin
elsif std_match(wb_master_out.adr, x"C0002---") then
slave := SLAVE_UART;
elsif std_match(wb_master_out.adr, x"C01-----") then
slave := SLAVE_DRAM_CSR;
slave := SLAVE_DRAM_CTRL;
elsif std_match(wb_master_out.adr, x"C0004---") then
slave := SLAVE_ICP_0;
end if;
@@ -204,7 +204,7 @@ begin
wb_dram_in <= wb_master_out;
wb_dram_in.cyc <= '0';
wb_dram_csr <= '0';
wb_dram_ctrl <= '0';
wb_dram_init <= '0';
wb_syscon_in <= wb_master_out;
wb_syscon_in.cyc <= '0';
@@ -219,10 +219,10 @@ begin
wb_dram_in.cyc <= wb_master_out.cyc;
wb_master_in <= wb_dram_out;
wb_dram_init <= '1';
when SLAVE_DRAM_CSR =>
when SLAVE_DRAM_CTRL =>
wb_dram_in.cyc <= wb_master_out.cyc;
wb_master_in <= wb_dram_out;
wb_dram_csr <= '1';
wb_dram_ctrl <= '1';
when SLAVE_SYSCON =>
wb_syscon_in.cyc <= wb_master_out.cyc;
wb_master_in <= wb_syscon_out;