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litedram: Update to new LiteX/LiteDRAM version

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Things have changed a bit in upstream LiteX. LiteDRAM now exposes a
wishbone for the CSRs for example.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2020-05-12 20:27:15 +10:00
parent 13e84b0bbb
commit c19b5b8cc7
20 changed files with 7250 additions and 6131 deletions
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6
fpga/top-arty.vhdl
View File

@@ -68,7 +68,7 @@ architecture behaviour of toplevel is
-- DRAM wishbone connection
signal wb_dram_in : wishbone_master_out;
signal wb_dram_out : wishbone_slave_out;
signal wb_dram_csr : std_ulogic;
signal wb_dram_ctrl : std_ulogic;
signal wb_dram_init : std_ulogic;
-- Control/status
@@ -104,7 +104,7 @@ begin
uart0_rxd => uart_main_rx,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_dram_csr => wb_dram_csr,
wb_dram_ctrl => wb_dram_ctrl,
wb_dram_init => wb_dram_init,
alt_reset => core_alt_reset
);
@@ -194,7 +194,7 @@ begin
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_is_csr => wb_dram_csr,
wb_is_ctrl => wb_dram_ctrl,
wb_is_init => wb_dram_init,
serial_tx => uart_pmod_tx,

6
fpga/top-nexys-video.vhdl
View File

@@ -60,7 +60,7 @@ architecture behaviour of toplevel is
-- DRAM wishbone connection
signal wb_dram_in : wishbone_master_out;
signal wb_dram_out : wishbone_slave_out;
signal wb_dram_csr : std_ulogic;
signal wb_dram_ctrl : std_ulogic;
signal wb_dram_init : std_ulogic;
-- Control/status
@@ -87,7 +87,7 @@ begin
uart0_rxd => uart_main_rx,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_dram_csr => wb_dram_csr,
wb_dram_ctrl => wb_dram_ctrl,
wb_dram_init => wb_dram_init,
alt_reset => core_alt_reset
);
@@ -175,7 +175,7 @@ begin
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_is_csr => wb_dram_csr,
wb_is_ctrl => wb_dram_ctrl,
wb_is_init => wb_dram_init,
serial_tx => open,