litesdcard: Regenerate verilog code with buffer direction controls

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This regenerates the verilog code from upstream litex plus a patch to
generate outputs from the litesdcard module for controlling
bidirectional buffers between the FPGA and SD card.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

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Paul Mackerras

2024-04-03 20:03:42 +11:00

parent 264e609fd4

commit c1f23e7417

2 changed files with 8340 additions and 7615 deletions

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litesdcard/generated/lattice.48e6/litesdcard_core.v

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litesdcard/generated/xilinx.100e6/litesdcard_core.v

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