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Make wishbone_master_out and wb_io_master_out match

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This makes it easier to parse the records in verilog because they
are getting flattened into an array of bits by ghdl/yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
2020-12-20 21:11:17 +11:00
committed by Anton Blanchard
parent d96ee21c39
commit c6dfc19d89
1 changed files with 1 additions and 1 deletions
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wishbone_types.vhdl
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@@ -16,9 +16,9 @@ package wishbone_types is
type wishbone_master_out is record
adr : wishbone_addr_type;
dat : wishbone_data_type;
sel : wishbone_sel_type;
cyc : std_ulogic;
stb : std_ulogic;
sel : wishbone_sel_type;
we : std_ulogic;
end record;
constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');