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Anton Blanchard
committed by
Anton Blanchard
Anton Blanchard
parent
601f3211be
commit
c76e638a77
280
rotator.vhdl
280
rotator.vhdl
@@ -7,17 +7,17 @@ use work.common.all;
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entity rotator is
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port (rs: in std_ulogic_vector(63 downto 0);
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ra: in std_ulogic_vector(63 downto 0);
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shift: in std_ulogic_vector(6 downto 0);
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insn: in std_ulogic_vector(31 downto 0);
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is_32bit: in std_ulogic;
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right_shift: in std_ulogic;
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arith: in std_ulogic;
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clear_left: in std_ulogic;
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clear_right: in std_ulogic;
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ra: in std_ulogic_vector(63 downto 0);
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shift: in std_ulogic_vector(6 downto 0);
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insn: in std_ulogic_vector(31 downto 0);
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is_32bit: in std_ulogic;
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right_shift: in std_ulogic;
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arith: in std_ulogic;
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clear_left: in std_ulogic;
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clear_right: in std_ulogic;
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sign_ext_rs: in std_ulogic;
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result: out std_ulogic_vector(63 downto 0);
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carry_out: out std_ulogic
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result: out std_ulogic_vector(63 downto 0);
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carry_out: out std_ulogic
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);
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end entity rotator;
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@@ -31,159 +31,159 @@ architecture behaviour of rotator is
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-- note BE bit numbering
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function right_mask(mask_begin: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
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variable ret: std_ulogic_vector(63 downto 0);
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variable ret: std_ulogic_vector(63 downto 0);
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begin
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ret := (others => '0');
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for i in 0 to 63 loop
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if i >= to_integer(unsigned(mask_begin)) then
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ret(63 - i) := '1';
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end if;
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end loop;
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return ret;
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ret := (others => '0');
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for i in 0 to 63 loop
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if i >= to_integer(unsigned(mask_begin)) then
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ret(63 - i) := '1';
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end if;
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end loop;
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return ret;
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end;
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function left_mask(mask_end: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
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variable ret: std_ulogic_vector(63 downto 0);
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variable ret: std_ulogic_vector(63 downto 0);
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begin
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ret := (others => '0');
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if mask_end(6) = '0' then
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for i in 0 to 63 loop
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if i <= to_integer(unsigned(mask_end)) then
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ret(63 - i) := '1';
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end if;
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end loop;
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end if;
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return ret;
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ret := (others => '0');
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if mask_end(6) = '0' then
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for i in 0 to 63 loop
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if i <= to_integer(unsigned(mask_end)) then
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ret(63 - i) := '1';
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end if;
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end loop;
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end if;
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return ret;
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end;
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begin
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rotator_0: process(all)
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variable hi32: std_ulogic_vector(31 downto 0);
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begin
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-- First replicate bottom 32 bits to both halves if 32-bit
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if is_32bit = '1' then
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-- First replicate bottom 32 bits to both halves if 32-bit
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if is_32bit = '1' then
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hi32 := rs(31 downto 0);
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elsif sign_ext_rs = '1' then
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elsif sign_ext_rs = '1' then
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-- sign extend bottom 32 bits
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hi32 := (others => rs(31));
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else
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hi32 := rs(63 downto 32);
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end if;
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hi32 := rs(63 downto 32);
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end if;
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repl32 <= hi32 & rs(31 downto 0);
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-- Negate shift count for right shifts
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if right_shift = '1' then
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rot_count <= std_ulogic_vector(- signed(shift(5 downto 0)));
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else
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rot_count <= shift(5 downto 0);
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end if;
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-- Negate shift count for right shifts
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if right_shift = '1' then
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rot_count <= std_ulogic_vector(- signed(shift(5 downto 0)));
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else
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rot_count <= shift(5 downto 0);
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end if;
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-- Rotator works in 3 stages using 2 bits of the rotate count each
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-- time. This gives 4:1 multiplexors which is ideal for the 6-input
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-- LUTs in the Xilinx Artix 7.
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-- We look at the low bits of the rotate count first because they will
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-- have less delay through the negation above.
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-- First rotate by 0, 1, 2, or 3
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case rot_count(1 downto 0) is
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when "00" =>
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rot1 <= repl32;
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when "01" =>
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rot1 <= repl32(62 downto 0) & repl32(63);
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when "10" =>
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rot1 <= repl32(61 downto 0) & repl32(63 downto 62);
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when others =>
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rot1 <= repl32(60 downto 0) & repl32(63 downto 61);
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end case;
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-- Next rotate by 0, 4, 8 or 12
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case rot_count(3 downto 2) is
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when "00" =>
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rot2 <= rot1;
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when "01" =>
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rot2 <= rot1(59 downto 0) & rot1(63 downto 60);
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when "10" =>
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rot2 <= rot1(55 downto 0) & rot1(63 downto 56);
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when others =>
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rot2 <= rot1(51 downto 0) & rot1(63 downto 52);
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end case;
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-- Lastly rotate by 0, 16, 32 or 48
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case rot_count(5 downto 4) is
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when "00" =>
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rot <= rot2;
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when "01" =>
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rot <= rot2(47 downto 0) & rot2(63 downto 48);
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when "10" =>
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rot <= rot2(31 downto 0) & rot2(63 downto 32);
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when others =>
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rot <= rot2(15 downto 0) & rot2(63 downto 16);
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end case;
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-- Rotator works in 3 stages using 2 bits of the rotate count each
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-- time. This gives 4:1 multiplexors which is ideal for the 6-input
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-- LUTs in the Xilinx Artix 7.
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-- We look at the low bits of the rotate count first because they will
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-- have less delay through the negation above.
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-- First rotate by 0, 1, 2, or 3
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case rot_count(1 downto 0) is
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when "00" =>
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rot1 <= repl32;
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when "01" =>
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rot1 <= repl32(62 downto 0) & repl32(63);
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when "10" =>
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rot1 <= repl32(61 downto 0) & repl32(63 downto 62);
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when others =>
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rot1 <= repl32(60 downto 0) & repl32(63 downto 61);
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end case;
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-- Next rotate by 0, 4, 8 or 12
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case rot_count(3 downto 2) is
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when "00" =>
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rot2 <= rot1;
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when "01" =>
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rot2 <= rot1(59 downto 0) & rot1(63 downto 60);
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when "10" =>
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rot2 <= rot1(55 downto 0) & rot1(63 downto 56);
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when others =>
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rot2 <= rot1(51 downto 0) & rot1(63 downto 52);
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end case;
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-- Lastly rotate by 0, 16, 32 or 48
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case rot_count(5 downto 4) is
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when "00" =>
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rot <= rot2;
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when "01" =>
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rot <= rot2(47 downto 0) & rot2(63 downto 48);
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when "10" =>
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rot <= rot2(31 downto 0) & rot2(63 downto 32);
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when others =>
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rot <= rot2(15 downto 0) & rot2(63 downto 16);
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end case;
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-- Trim shift count to 6 bits for 32-bit shifts
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sh <= (shift(6) and not is_32bit) & shift(5 downto 0);
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-- Trim shift count to 6 bits for 32-bit shifts
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sh <= (shift(6) and not is_32bit) & shift(5 downto 0);
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-- Work out mask begin/end indexes (caution, big-endian bit numbering)
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if clear_left = '1' then
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if is_32bit = '1' then
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mb <= "01" & insn(10 downto 6);
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else
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mb <= "0" & insn(5) & insn(10 downto 6);
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end if;
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elsif right_shift = '1' then
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-- this is basically mb <= sh + (is_32bit? 32: 0);
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if is_32bit = '1' then
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mb <= sh(5) & not sh(5) & sh(4 downto 0);
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else
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mb <= sh;
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end if;
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else
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mb <= ('0' & is_32bit & "00000");
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end if;
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if clear_right = '1' and is_32bit = '1' then
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me <= "01" & insn(5 downto 1);
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elsif clear_right = '1' and clear_left = '0' then
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me <= "0" & insn(5) & insn(10 downto 6);
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else
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-- effectively, 63 - sh
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me <= sh(6) & not sh(5 downto 0);
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end if;
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-- Work out mask begin/end indexes (caution, big-endian bit numbering)
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if clear_left = '1' then
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if is_32bit = '1' then
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mb <= "01" & insn(10 downto 6);
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else
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mb <= "0" & insn(5) & insn(10 downto 6);
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end if;
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elsif right_shift = '1' then
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-- this is basically mb <= sh + (is_32bit? 32: 0);
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if is_32bit = '1' then
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mb <= sh(5) & not sh(5) & sh(4 downto 0);
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else
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mb <= sh;
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end if;
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else
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mb <= ('0' & is_32bit & "00000");
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end if;
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if clear_right = '1' and is_32bit = '1' then
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me <= "01" & insn(5 downto 1);
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elsif clear_right = '1' and clear_left = '0' then
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me <= "0" & insn(5) & insn(10 downto 6);
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else
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-- effectively, 63 - sh
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me <= sh(6) & not sh(5 downto 0);
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end if;
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-- Calculate left and right masks
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mr <= right_mask(mb);
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ml <= left_mask(me);
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-- Calculate left and right masks
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mr <= right_mask(mb);
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ml <= left_mask(me);
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-- Work out output mode
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-- 00 for sl[wd]
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-- 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
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-- 10 for rldicl, sr[wd]
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-- 1z for sra[wd][i], z = 1 if rs is negative
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if (clear_left = '1' and clear_right = '0') or right_shift = '1' then
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output_mode(1) <= '1';
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output_mode(0) <= arith and repl32(63);
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else
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output_mode(1) <= '0';
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if clear_right = '1' and unsigned(mb(5 downto 0)) > unsigned(me(5 downto 0)) then
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output_mode(0) <= '1';
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else
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output_mode(0) <= '0';
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end if;
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end if;
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-- Work out output mode
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-- 00 for sl[wd]
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-- 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
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-- 10 for rldicl, sr[wd]
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-- 1z for sra[wd][i], z = 1 if rs is negative
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if (clear_left = '1' and clear_right = '0') or right_shift = '1' then
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output_mode(1) <= '1';
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output_mode(0) <= arith and repl32(63);
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else
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output_mode(1) <= '0';
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if clear_right = '1' and unsigned(mb(5 downto 0)) > unsigned(me(5 downto 0)) then
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output_mode(0) <= '1';
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else
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output_mode(0) <= '0';
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end if;
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end if;
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-- Generate output from rotated input and masks
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case output_mode is
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when "00" =>
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result <= (rot and (mr and ml)) or (ra and not (mr and ml));
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when "01" =>
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result <= (rot and (mr or ml)) or (ra and not (mr or ml));
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when "10" =>
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result <= rot and mr;
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when others =>
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result <= rot or not mr;
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end case;
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-- Generate output from rotated input and masks
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case output_mode is
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when "00" =>
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result <= (rot and (mr and ml)) or (ra and not (mr and ml));
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when "01" =>
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result <= (rot and (mr or ml)) or (ra and not (mr or ml));
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when "10" =>
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result <= rot and mr;
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when others =>
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result <= rot or not mr;
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end case;
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-- Generate carry output for arithmetic shift right of negative value
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if output_mode = "11" then
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carry_out <= or (rs and not ml);
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else
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carry_out <= '0';
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end if;
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-- Generate carry output for arithmetic shift right of negative value
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if output_mode = "11" then
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carry_out <= or (rs and not ml);
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else
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carry_out <= '0';
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end if;
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end process;
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end behaviour;
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