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Merge pull request #46 from antonblanchard/record-fix

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Remove names from end record statements
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Anton Blanchard 2019-09-12 09:46:01 +10:00 committed by GitHub
commit ca6f84efd6
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3 changed files with 4 additions and 4 deletions
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2
fpga/clk_gen_mcmm.vhd
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@ -22,7 +22,7 @@ architecture rtl of clock_generator is
clkfbout_mult : real range 2.0 to 64.0;
clkout_divide : real range 1.0 to 128.0;
divclk_divide : integer range 1 to 106;
end record pll_settings_t;
end record;
function gen_pll_settings (
constant freq_hz : positive)

2
fpga/clk_gen_plle2.vhd
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@ -23,7 +23,7 @@ architecture rtl of clock_generator is
clkfbout_mult : integer range 2 to 64;
clkout_divide : integer range 1 to 128;
divclk_divide : integer range 1 to 56;
end record pll_settings_t;
end record;
function gen_pll_settings (
constant freq_hz : positive)

4
wishbone_types.vhdl
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@ -15,13 +15,13 @@ package wishbone_types is
stb : std_ulogic;
sel : std_ulogic_vector(7 downto 0);
we : std_ulogic;
end record wishbone_master_out;
end record;
constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0'));
type wishbone_slave_out is record
dat : wishbone_data_type;
ack : std_ulogic;
end record wishbone_slave_out;
end record;
constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0'));
end package wishbone_types;