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https://github.com/antonblanchard/microwatt.git
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Metavalue cleanup for common.vhdl
This affects other files which have been included here. Signed-off-by: Michael Neuling <mikey@neuling.org>
This commit is contained in:
Michael Neuling
35
common.vhdl
35
common.vhdl
@@ -115,28 +115,29 @@ package common is
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-- Some SPRs are stored in a pair of small RAMs in execute1
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-- Even half:
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subtype ramspr_index is natural range 0 to 7;
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constant RAMSPR_SRR0 : ramspr_index := 0;
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constant RAMSPR_HSRR0 : ramspr_index := 1;
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constant RAMSPR_SPRG0 : ramspr_index := 2;
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constant RAMSPR_SPRG2 : ramspr_index := 3;
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constant RAMSPR_HSPRG0 : ramspr_index := 4;
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constant RAMSPR_LR : ramspr_index := 5; -- must equal RAMSPR_CTR
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constant RAMSPR_TAR : ramspr_index := 6;
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subtype ramspr_index_range is natural range 0 to 7;
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subtype ramspr_index is unsigned(2 downto 0);
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constant RAMSPR_SRR0 : ramspr_index := to_unsigned(0,3);
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constant RAMSPR_HSRR0 : ramspr_index := to_unsigned(1,3);
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constant RAMSPR_SPRG0 : ramspr_index := to_unsigned(2,3);
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constant RAMSPR_SPRG2 : ramspr_index := to_unsigned(3,3);
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constant RAMSPR_HSPRG0 : ramspr_index := to_unsigned(4,3);
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constant RAMSPR_LR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_CTR
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constant RAMSPR_TAR : ramspr_index := to_unsigned(6,3);
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-- Odd half:
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constant RAMSPR_SRR1 : ramspr_index := 0;
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constant RAMSPR_HSRR1 : ramspr_index := 1;
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constant RAMSPR_SPRG1 : ramspr_index := 2;
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constant RAMSPR_SPRG3 : ramspr_index := 3;
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constant RAMSPR_HSPRG1 : ramspr_index := 4;
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constant RAMSPR_CTR : ramspr_index := 5; -- must equal RAMSPR_LR
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constant RAMSPR_SRR1 : ramspr_index := to_unsigned(0,3);
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constant RAMSPR_HSRR1 : ramspr_index := to_unsigned(1,3);
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constant RAMSPR_SPRG1 : ramspr_index := to_unsigned(2,3);
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constant RAMSPR_SPRG3 : ramspr_index := to_unsigned(3,3);
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constant RAMSPR_HSPRG1 : ramspr_index := to_unsigned(4,3);
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constant RAMSPR_CTR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_LR
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type ram_spr_info is record
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index : ramspr_index;
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isodd : std_ulogic;
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valid : std_ulogic;
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end record;
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constant ram_spr_info_init: ram_spr_info := (index => 0, others => '0');
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constant ram_spr_info_init: ram_spr_info := (index => to_unsigned(0,3), others => '0');
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subtype spr_selector is std_ulogic_vector(2 downto 0);
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type spr_id is record
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@@ -366,8 +367,8 @@ package common is
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result_sel => "000", sub_select => "000",
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repeat => '0', second => '0', spr_select => spr_id_init,
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spr_is_ram => '0',
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ramspr_even_rdaddr => 0, ramspr_odd_rdaddr => 0, ramspr_rd_odd => '0',
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ramspr_wraddr => 0, ramspr_write_even => '0', ramspr_write_odd => '0',
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ramspr_even_rdaddr => (others => '0'), ramspr_odd_rdaddr => (others => '0'), ramspr_rd_odd => '0',
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ramspr_wraddr => (others => '0'), ramspr_write_even => '0', ramspr_write_odd => '0',
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dbg_spr_access => '0',
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dec_ctr => '0',
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others => (others => '0'));
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@@ -273,7 +273,7 @@ begin
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valid := '1';
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sel := "000";
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isram := '1';
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raddr := 0;
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raddr := (others => '0');
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odd := '0';
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case gspr_index(4 downto 0) is
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when 5x"00" =>
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@@ -304,7 +304,7 @@ begin
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when others =>
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valid := '0';
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end case;
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dbg_spr_addr <= isram & sel & std_ulogic_vector(to_unsigned(raddr, 3)) & odd;
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dbg_spr_addr <= isram & sel & std_ulogic_vector(raddr) & odd;
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spr_index_valid <= valid;
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end if;
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end process;
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@@ -530,7 +530,7 @@ architecture behaviour of decode1 is
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function decode_ram_spr(sprn : spr_num_t) return ram_spr_info is
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variable ret : ram_spr_info;
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begin
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ret := (index => 0, isodd => '0', valid => '1');
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ret := (index => (others => '0'), isodd => '0', valid => '1');
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case sprn is
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when SPR_LR =>
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ret.index := RAMSPR_LR;
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@@ -671,8 +671,8 @@ begin
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v.e.dbg_spr_access := dbg_spr_req and not v.read_rspr;
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if v.e.dbg_spr_access = '1' then
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v.e.ramspr_even_rdaddr := to_integer(unsigned(dbg_spr_addr(3 downto 1)));
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v.e.ramspr_odd_rdaddr := to_integer(unsigned(dbg_spr_addr(3 downto 1)));
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v.e.ramspr_even_rdaddr := unsigned(dbg_spr_addr(3 downto 1));
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v.e.ramspr_odd_rdaddr := unsigned(dbg_spr_addr(3 downto 1));
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v.e.ramspr_rd_odd := dbg_spr_addr(0);
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end if;
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@@ -147,7 +147,7 @@ architecture behaviour of execute1 is
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taken_branch_event => '0', br_mispredict => '0',
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msr => 64x"0",
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xerc => xerc_init, xerc_valid => '0',
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ramspr_wraddr => 0, ramspr_odd_data => 64x"0");
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ramspr_wraddr => (others => '0'), ramspr_odd_data => 64x"0");
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type reg_stage2_type is record
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e : Execute1ToWritebackType;
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@@ -221,7 +221,7 @@ architecture behaviour of execute1 is
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signal irq_valid_log : std_ulogic;
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-- SPR-related signals
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type ramspr_half_t is array(ramspr_index) of std_ulogic_vector(63 downto 0);
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type ramspr_half_t is array(ramspr_index_range) of std_ulogic_vector(63 downto 0);
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signal even_sprs : ramspr_half_t := (others => (others => '0'));
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signal odd_sprs : ramspr_half_t := (others => (others => '0'));
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signal ramspr_even : std_ulogic_vector(63 downto 0);
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@@ -510,8 +510,16 @@ begin
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variable doit : std_ulogic;
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begin
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-- Read address mux and async RAM reading
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even_rd_data := even_sprs(e_in.ramspr_even_rdaddr);
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odd_rd_data := odd_sprs(e_in.ramspr_odd_rdaddr);
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if is_X(e_in.ramspr_even_rdaddr) then
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even_rd_data := (others => 'X');
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else
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even_rd_data := even_sprs(to_integer(e_in.ramspr_even_rdaddr));
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end if;
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if is_X(e_in.ramspr_even_rdaddr) then
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odd_rd_data := (others => 'X');
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else
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odd_rd_data := odd_sprs(to_integer(e_in.ramspr_odd_rdaddr));
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end if;
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-- Write address and data muxes
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doit := ex1.e.valid and not stage2_stall and not flush_in;
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@@ -559,13 +567,15 @@ begin
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begin
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if rising_edge(clk) then
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if ramspr_even_wr_enab = '1' then
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even_sprs(ramspr_wr_addr) <= ramspr_even_wr_data;
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report "writing even spr " & integer'image(ramspr_wr_addr) & " data=" &
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assert not is_X(ramspr_wr_addr) report "Writing to unknown address" severity FAILURE;
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even_sprs(to_integer(ramspr_wr_addr)) <= ramspr_even_wr_data;
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report "writing even spr " & integer'image(to_integer(ramspr_wr_addr)) & " data=" &
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to_hstring(ramspr_even_wr_data);
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end if;
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if ramspr_odd_wr_enab = '1' then
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odd_sprs(ramspr_wr_addr) <= ramspr_odd_wr_data;
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report "writing odd spr " & integer'image(ramspr_wr_addr) & " data=" &
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assert not is_X(ramspr_wr_addr) report "Writing to unknown address" severity FAILURE;
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odd_sprs(to_integer(ramspr_wr_addr)) <= ramspr_odd_wr_data;
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report "writing odd spr " & integer'image(to_integer(ramspr_wr_addr)) & " data=" &
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to_hstring(ramspr_odd_wr_data);
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end if;
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end if;
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@@ -1773,8 +1783,8 @@ begin
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variable xer : std_ulogic_vector(63 downto 0);
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begin
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if sim_dump = '1' then
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report "LR " & to_hstring(even_sprs(RAMSPR_LR));
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report "CTR " & to_hstring(odd_sprs(RAMSPR_CTR));
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report "LR " & to_hstring(even_sprs(to_integer(RAMSPR_LR)));
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report "CTR " & to_hstring(odd_sprs(to_integer(RAMSPR_CTR)));
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sim_dump_done <= '1';
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else
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sim_dump_done <= '0';
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