litedram: Add generator for Genesys2

(Not yet generated)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

litedram/gen-src/generate.py

@@ -143,7 +143,7 @@ def generate_one(t):
 
 def main():
 
-    targets = ['arty','nexys-video', 'sim']
+    targets = ['arty','nexys-video', 'genesys2', 'sim']
     for t in targets:
         generate_one(t)
     

litedram/gen-src/genesys2.yml

@@ -0,0 +1,41 @@
+# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+{
+    # General ------------------------------------------------------------------
+    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
+    "cpu_variant":"standard",
+    "speedgrade": -2,          # FPGA speedgrade
+    "memtype":    "DDR3",      # DRAM type
+
+    # PHY ----------------------------------------------------------------------
+    "cmd_latency":     0,             # Command additional latency
+    "sdram_module":    "MT41J256M16", # SDRAM modules of the board or SO-DIMM
+    "sdram_module_nb": 4,             # Number of byte groups
+    "sdram_rank_nb":   1,             # Number of ranks
+    "sdram_phy":       K7DDRPHY,      # Type of FPGA PHY
+
+    # Electrical ---------------------------------------------------------------
+    "rtt_nom": "60ohm", # Nominal termination
+    "rtt_wr":  "60ohm", # Write termination
+    "ron":     "34ohm", # Output driver impedance
+
+    # Frequency ----------------------------------------------------------------
+    "input_clk_freq":   200e6, # Input clock frequency
+    "sys_clk_freq":     100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+    "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
+
+    # Core ---------------------------------------------------------------------
+    "cmd_buffer_depth": 16,    # Depth of the command buffer
+
+    # User Ports ---------------------------------------------------------------
+    "user_ports": {
+        "native_0": {
+            "type": "native",
+        },
+    },
+
+    # CSR Port -----------------------------------------------------------------
+    "csr_alignment"  : 32,
+    "csr_data_width" : 32,
+}