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orangecrab: No BTC, LOG_LENGTH, dram NUM_LINES

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Reduce litedram NUM_LINES 64->8
This allows us to meet timing. Can probably
be improved in future with better BRAM usage.

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
This commit is contained in:
Matt Johnston
2021-08-23 10:30:40 +08:00
parent a8d9203c5d
commit d794cc70b1
1 changed files with 4 additions and 3 deletions
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7
fpga/top-orangecrab0.2.vhdl
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@@ -13,19 +13,19 @@ entity toplevel is
CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000;
HAS_FPU : boolean := true;
HAS_BTC : boolean := true;
HAS_BTC : boolean := false;
USE_LITEDRAM : boolean := true;
NO_BRAM : boolean := true;
SCLK_STARTUPE2 : boolean := false;
SPI_FLASH_OFFSET : integer := 4194304;
SPI_FLASH_DEF_CKDV : natural := 1;
SPI_FLASH_DEF_QUAD : boolean := true;
LOG_LENGTH : natural := 512;
LOG_LENGTH : natural := 0;
UART_IS_16550 : boolean := true;
HAS_UART1 : boolean := true;
USE_LITESDCARD : boolean := false;
ICACHE_NUM_LINES : natural := 64;
NGPIO : natural := 32
NGPIO : natural := 0
);
port(
ext_clk : in std_ulogic;
@@ -332,6 +332,7 @@ begin
DRAM_ALINES => 14,
DRAM_DLINES => 16,
DRAM_PORT_WIDTH => 128,
NUM_LINES => 8, -- reduce from default of 64 to make smaller/timing
PAYLOAD_FILE => RAM_INIT_FILE,
PAYLOAD_SIZE => PAYLOAD_SIZE
)