mirror of
https://github.com/antonblanchard/microwatt.git
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Merge pull request #278 from shenki/openocd-v0.11
Add files for openocd v0.11
This commit is contained in:
@@ -23,10 +23,11 @@ Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part
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Error: Unknown flash device (ID 0x00ffffff)
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If you find yourself with a later openocd version that contians 867bdb2e9248
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("jtagspi: new protocol that includes transfer length") you should fetch the
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bitstream from the master branch:
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("jtagspi: new protocol that includes transfer length"), such as v0.11 as
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packaged by Debian Bullseye, you should use the bitstream from the master
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branch:
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https://github.com/quartiq/bscan_spi_bitstreams/blob/master/bscan_spi_xc7a35t.bit?raw=true
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https://github.com/quartiq/bscan_spi_bitstreams/blob/master/bscan_spi_xc7a100t.bit?raw=true
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These are in the microwatt repository as bscan_spi_xc7a*t_openocd_v0.11.bit.
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BIN
openocd/bscan_spi_xc7a100t_openocd_v0.11.bit
Normal file
BIN
openocd/bscan_spi_xc7a100t_openocd_v0.11.bit
Normal file
Binary file not shown.
BIN
openocd/bscan_spi_xc7a200t_openocd_v0.11.bit
Normal file
BIN
openocd/bscan_spi_xc7a200t_openocd_v0.11.bit
Normal file
Binary file not shown.
BIN
openocd/bscan_spi_xc7a35t_openocd_v0.11.bit
Normal file
BIN
openocd/bscan_spi_xc7a35t_openocd_v0.11.bit
Normal file
Binary file not shown.
@@ -6,7 +6,6 @@ import subprocess
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import sys
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BASE = os.path.dirname(os.path.abspath(__file__))
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CONFIG = os.path.join(BASE, "xilinx-xc7.cfg")
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def flash(config, flash_proxy, address, data, filetype="", set_qe=False):
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script = "; ".join([
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@@ -20,6 +19,15 @@ def flash(config, flash_proxy, address, data, filetype="", set_qe=False):
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print(script)
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subprocess.call(["openocd", "-f", config, "-c", script])
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def get_version():
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a = subprocess.run(["openocd", "-v"], capture_output=True)
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if a.returncode != 0:
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return ""
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if a.stderr.count(b"0.10"):
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return ""
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if a.stderr.count(b"0.11"):
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return "_openocd_v0.11"
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parser = argparse.ArgumentParser()
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parser.add_argument("file", help="file to write to flash")
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parser.add_argument("-a", "--address", help="offset in flash", type=lambda x: int(x,0), default=0)
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@@ -27,16 +35,19 @@ parser.add_argument("-f", "--fpga", help="a35, a100 or a200", default="a35")
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parser.add_argument("-t", "--filetype", help="file type such as 'bin'", default="")
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args = parser.parse_args()
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version = get_version()
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if args.fpga.lower() == "a35":
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proxy = "bscan_spi_xc7a35t.bit"
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proxy = "bscan_spi_xc7a35t{}.bit".format(version)
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elif args.fpga.lower() == "a100":
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proxy = "bscan_spi_xc7a100t.bit"
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proxy = "bscan_spi_xc7a100t{}.bit".format(version)
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elif args.fpga.lower() == "a200":
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proxy = "bscan_spi_xc7a200t.bit"
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proxy = "bscan_spi_xc7a200t{}.bit".format(version)
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else:
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print("error: specify a35, a100 or a200 when flashing")
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sys.exit()
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proxy = os.path.join(BASE, proxy)
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config = os.path.join(BASE, "xilinx-xc7{}.cfg".format(version))
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flash(CONFIG, proxy, args.address, args.file, args.filetype.lower())
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flash(config, proxy, args.address, args.file, args.filetype.lower())
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68
openocd/xilinx-xc7_openocd_v0.11.cfg
Normal file
68
openocd/xilinx-xc7_openocd_v0.11.cfg
Normal file
@@ -0,0 +1,68 @@
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# This file is the same sa xilinx-xc7.cfg, except we use
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# verify_image instead of verify_bank
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_channel 0
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ftdi_layout_init 0x00e8 0x60eb
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reset_config none
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adapter_khz 25000
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source [find cpld/xilinx-xc7.cfg]
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# From jtagspi.cfg with modification to support
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# specifying file type
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set _USER1 0x02
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if { [info exists JTAGSPI_IR] } {
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set _JTAGSPI_IR $JTAGSPI_IR
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} else {
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set _JTAGSPI_IR $_USER1
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}
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if { [info exists DR_LENGTH] } {
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set _DR_LENGTH $DR_LENGTH
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} else {
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set _DR_LENGTH 1
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}
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if { [info exists TARGETNAME] } {
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set _TARGETNAME $TARGETNAME
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} else {
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set _TARGETNAME $_CHIPNAME.proxy
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}
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if { [info exists FLASHNAME] } {
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set _FLASHNAME $FLASHNAME
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} else {
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set _FLASHNAME $_CHIPNAME.spi
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}
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target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
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flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
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proc jtagspi_init {chain_id proxy_bit} {
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# load proxy bitstream $proxy_bit and probe spi flash
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global _FLASHNAME
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pld load $chain_id $proxy_bit
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reset halt
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flash probe $_FLASHNAME
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}
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proc jtagspi_program {bin addr {type ""} } {
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# write and verify binary file $bin at offset $addr
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global _FLASHNAME
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if { $type eq "" } {
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flash write_image erase $bin $addr
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flash verify_image $bin $addr
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} else {
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flash write_image erase $bin $addr $type
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flash verify_image $bin $addr $type
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}
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}
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# end jtagspi.cfg
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proc fpga_program {} {
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global _CHIPNAME
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xc7_program $_CHIPNAME.tap
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}
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