mirror of
https://github.com/antonblanchard/microwatt.git
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FPU: Implement floating multiply-add instructions
This implements fmadd, fmsub, fnmadd, fnmsub and their single-precision counterparts. The single-precision versions operate the same as the double-precision versions until the final rounding and overflow/underflow steps. This adds an S register to store the low bits of the product. S shifts into R on left shifts, and can be negated, but doesn't do any other arithmetic. This adds a test for the double-precision versions of these instructions. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
@@ -423,6 +423,10 @@ architecture behaviour of decode1 is
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2#11000# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- fres
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2#11001# => (FPU, OP_FPOP, FRA, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- fmuls
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2#11010# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- frsqrtes
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2#11100# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- fmsubs
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2#11101# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- fmadds
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2#11110# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- fnmsubs
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2#11111# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- fnmadds
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others => illegal_inst
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);
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@@ -485,6 +489,10 @@ architecture behaviour of decode1 is
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2#1000# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- fre
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2#1001# => (FPU, OP_FPOP, FRA, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- fmul
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2#1010# => (FPU, OP_FPOP, NONE, FRB, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- frsqrte
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2#1100# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- fmsub
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2#1101# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- fmadd
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2#1110# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- fnmsub
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2#1111# => (FPU, OP_FPOP, FRA, FRB, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- fnmadd
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others => illegal_inst
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);
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244
fpu.vhdl
244
fpu.vhdl
@@ -40,13 +40,15 @@ architecture behaviour of fpu is
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DO_FMR, DO_FMRG, DO_FCMP, DO_FTDIV, DO_FTSQRT,
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DO_FCFID, DO_FCTI,
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DO_FRSP, DO_FRI,
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DO_FADD, DO_FMUL, DO_FDIV, DO_FSQRT,
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DO_FADD, DO_FMUL, DO_FDIV, DO_FSQRT, DO_FMADD,
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DO_FRE, DO_FRSQRTE,
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DO_FSEL,
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FRI_1,
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ADD_SHIFT, ADD_2, ADD_3,
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CMP_1, CMP_2,
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MULT_1,
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FMADD_1, FMADD_2, FMADD_3,
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FMADD_4, FMADD_5, FMADD_6,
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LOOKUP,
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DIV_2, DIV_3, DIV_4, DIV_5, DIV_6,
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FRE_1,
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@@ -82,6 +84,7 @@ architecture behaviour of fpu is
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b : fpu_reg_type;
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c : fpu_reg_type;
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r : std_ulogic_vector(63 downto 0); -- 10.54 format
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s : std_ulogic_vector(55 downto 0); -- extended fraction
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x : std_ulogic;
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p : std_ulogic_vector(63 downto 0); -- 8.56 format
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y : std_ulogic_vector(63 downto 0); -- 8.56 format
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@@ -101,6 +104,7 @@ architecture behaviour of fpu is
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round_mode : std_ulogic_vector(2 downto 0);
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is_subtract : std_ulogic;
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exp_cmp : std_ulogic;
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madd_cmp : std_ulogic;
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add_bsmall : std_ulogic;
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is_multiply : std_ulogic;
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is_sqrt : std_ulogic;
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@@ -117,6 +121,7 @@ architecture behaviour of fpu is
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signal opsel_a : std_ulogic_vector(1 downto 0);
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signal opsel_b : std_ulogic_vector(1 downto 0);
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signal opsel_r : std_ulogic_vector(1 downto 0);
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signal opsel_s : std_ulogic_vector(1 downto 0);
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signal opsel_ainv : std_ulogic;
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signal opsel_amask : std_ulogic;
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signal opsel_binv : std_ulogic;
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@@ -127,6 +132,7 @@ architecture behaviour of fpu is
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signal lost_bits : std_ulogic;
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signal r_hi_nz : std_ulogic;
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signal r_lo_nz : std_ulogic;
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signal s_nz : std_ulogic;
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signal misc_sel : std_ulogic_vector(3 downto 0);
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signal f_to_multiply : MultiplyInputType;
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signal multiply_to_f : MultiplyOutputType;
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@@ -152,6 +158,11 @@ architecture behaviour of fpu is
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constant RES_MULT : std_ulogic_vector(1 downto 0) := "10";
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constant RES_MISC : std_ulogic_vector(1 downto 0) := "11";
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constant S_ZERO : std_ulogic_vector(1 downto 0) := "00";
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constant S_NEG : std_ulogic_vector(1 downto 0) := "01";
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constant S_SHIFT : std_ulogic_vector(1 downto 0) := "10";
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constant S_MULT : std_ulogic_vector(1 downto 0) := "11";
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-- msel values
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constant MUL1_A : std_ulogic_vector(1 downto 0) := "00";
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constant MUL1_B : std_ulogic_vector(1 downto 0) := "01";
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@@ -163,9 +174,10 @@ architecture behaviour of fpu is
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constant MUL2_P : std_ulogic_vector(1 downto 0) := "10";
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constant MUL2_R : std_ulogic_vector(1 downto 0) := "11";
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constant MULADD_ZERO : std_ulogic_vector(1 downto 0) := "00";
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constant MULADD_ZERO : std_ulogic_vector(1 downto 0) := "00";
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constant MULADD_CONST : std_ulogic_vector(1 downto 0) := "01";
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constant MULADD_A : std_ulogic_vector(1 downto 0) := "10";
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constant MULADD_RS : std_ulogic_vector(1 downto 0) := "11";
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-- Inverse lookup table, indexed by the top 8 fraction bits
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-- The first 256 entries are the reciprocal (1/x) lookup table,
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@@ -597,20 +609,22 @@ begin
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variable need_check : std_ulogic;
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variable msb : std_ulogic;
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variable is_add : std_ulogic;
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variable qnan_result : std_ulogic;
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variable longmask : std_ulogic;
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variable set_a : std_ulogic;
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variable set_b : std_ulogic;
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variable set_c : std_ulogic;
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variable px_nz : std_ulogic;
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variable maddend : std_ulogic_vector(127 downto 0);
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variable set_y : std_ulogic;
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variable set_s : std_ulogic;
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variable qnan_result : std_ulogic;
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variable px_nz : std_ulogic;
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variable pcmpb_eq : std_ulogic;
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variable pcmpb_lt : std_ulogic;
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variable pshift : std_ulogic;
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variable renorm_sqrt : std_ulogic;
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variable sqrt_exp : signed(EXP_BITS-1 downto 0);
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variable shiftin : std_ulogic;
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variable mulexp : signed(EXP_BITS-1 downto 0);
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variable maddend : std_ulogic_vector(127 downto 0);
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begin
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v := r;
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illegal := '0';
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@@ -657,10 +671,15 @@ begin
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if adec.exponent > bdec.exponent then
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v.exp_cmp := '1';
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end if;
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v.madd_cmp := '0';
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if (adec.exponent + cdec.exponent + 1) >= bdec.exponent then
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v.madd_cmp := '1';
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end if;
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end if;
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r_hi_nz <= or (r.r(55 downto 31));
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r_lo_nz <= or (r.r(30 downto 2));
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s_nz <= or (r.s);
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if r.single_prec = '0' then
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if r.doing_ftdiv(1) = '0' then
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@@ -711,6 +730,7 @@ begin
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opsel_b <= BIN_ZERO;
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opsel_binv <= '0';
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opsel_r <= RES_SUM;
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opsel_s <= S_ZERO;
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carry_in <= '0';
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misc_sel <= "0000";
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fpscr_mask := (others => '1');
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@@ -725,6 +745,7 @@ begin
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set_a := '0';
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set_b := '0';
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set_c := '0';
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set_s := '0';
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f_to_multiply.is_32bit <= '0';
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f_to_multiply.valid <= '0';
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msel_1 <= MUL1_A;
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@@ -802,12 +823,15 @@ begin
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when "11010" =>
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v.is_sqrt := '1';
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v.state := DO_FRSQRTE;
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when "11100" | "11101" | "11110" | "11111" =>
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v.state := DO_FMADD;
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when others =>
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illegal := '1';
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end case;
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end if;
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v.x := '0';
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v.old_exc := r.fpscr(FPSCR_VX downto FPSCR_XX);
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set_s := '1';
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when DO_MCRFS =>
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j := to_integer(unsigned(insn_bfa(r.insn)));
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@@ -1416,6 +1440,99 @@ begin
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arith_done := '1';
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end case;
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when DO_FMADD =>
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-- fmadd, fmsub, fnmadd, fnmsub
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opsel_a <= AIN_A;
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v.result_sign := r.a.negative;
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v.result_class := r.a.class;
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v.result_exp := r.a.exponent;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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is_add := r.a.negative xor r.c.negative xor r.b.negative xor r.insn(1);
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if r.a.class = FINITE and r.c.class = FINITE and
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(r.b.class = FINITE or r.b.class = ZERO) then
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v.is_subtract := not is_add;
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mulexp := r.a.exponent + r.c.exponent;
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v.result_exp := mulexp;
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opsel_a <= AIN_B;
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-- Make sure A and C are normalized
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if r.a.mantissa(54) = '0' then
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opsel_a <= AIN_A;
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v.state := RENORM_A;
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elsif r.c.mantissa(54) = '0' then
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opsel_a <= AIN_C;
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v.state := RENORM_C;
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elsif r.b.class = ZERO then
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-- no addend, degenerates to multiply
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v.result_sign := r.a.negative xor r.c.negative xor r.insn(2);
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f_to_multiply.valid <= '1';
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v.is_multiply := '1';
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v.state := MULT_1;
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elsif r.madd_cmp = '0' then
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-- addend is bigger, do multiply first
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v.result_sign := not (r.b.negative xor r.insn(1) xor r.insn(2));
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f_to_multiply.valid <= '1';
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v.state := FMADD_1;
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else
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-- product is bigger, shift B right and use it as the
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-- addend to the multiplier
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v.shift := r.b.exponent - mulexp + to_signed(64, EXP_BITS);
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-- for subtract, multiplier does B - A * C
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v.result_sign := not (r.a.negative xor r.c.negative xor r.insn(2) xor is_add);
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v.result_exp := r.b.exponent;
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v.state := FMADD_2;
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end if;
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else
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if (r.a.class = NAN and r.a.mantissa(53) = '0') or
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(r.b.class = NAN and r.b.mantissa(53) = '0') or
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(r.c.class = NAN and r.c.mantissa(53) = '0') then
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-- Signalling NAN
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v.fpscr(FPSCR_VXSNAN) := '1';
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invalid := '1';
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end if;
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if r.a.class = NAN then
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-- nothing to do, result is A
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elsif r.b.class = NAN then
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-- result is B
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v.result_class := NAN;
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v.result_sign := r.b.negative;
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opsel_a <= AIN_B;
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elsif r.c.class = NAN then
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-- result is C
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v.result_class := NAN;
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v.result_sign := r.c.negative;
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opsel_a <= AIN_C;
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elsif (r.a.class = ZERO and r.c.class = INFINITY) or
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(r.a.class = INFINITY and r.c.class = ZERO) then
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-- invalid operation, construct QNaN
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v.fpscr(FPSCR_VXIMZ) := '1';
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qnan_result := '1';
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elsif r.a.class = INFINITY or r.c.class = INFINITY then
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if r.b.class = INFINITY and is_add = '0' then
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-- invalid operation, construct QNaN
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v.fpscr(FPSCR_VXISI) := '1';
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qnan_result := '1';
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else
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-- result is infinity
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v.result_class := INFINITY;
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v.result_sign := r.a.negative xor r.c.negative xor r.insn(2);
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end if;
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else
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-- Here A is zero, C is zero, or B is infinity
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-- Result is +/-B in all of those cases
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v.result_class := r.b.class;
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v.result_exp := r.b.exponent;
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if v.result_class /= ZERO or is_add = '1' then
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v.result_sign := not (r.b.negative xor r.insn(1) xor r.insn(2));
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else
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-- have to be careful about rule for 0 - 0 result sign
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v.result_sign := (r.round_mode(1) and r.round_mode(0)) xor r.insn(2);
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end if;
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opsel_a <= AIN_B;
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end if;
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arith_done := '1';
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end if;
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when RENORM_A =>
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renormalize := '1';
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v.state := RENORM_A2;
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@@ -1426,8 +1543,16 @@ begin
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if r.insn(4) = '1' then
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opsel_a <= AIN_C;
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if r.c.mantissa(54) = '1' then
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v.first := '1';
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v.state := MULT_1;
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if r.insn(3) = '0' or r.b.class = ZERO then
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v.first := '1';
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v.state := MULT_1;
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else
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v.madd_cmp := '0';
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if new_exp + 1 >= r.b.exponent then
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v.madd_cmp := '1';
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end if;
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v.state := DO_FMADD;
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end if;
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else
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v.state := RENORM_C;
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end if;
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@@ -1462,11 +1587,20 @@ begin
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when RENORM_C2 =>
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set_c := '1';
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v.result_exp := new_exp;
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v.first := '1';
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v.state := MULT_1;
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if r.insn(3) = '0' or r.b.class = ZERO then
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v.first := '1';
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v.state := MULT_1;
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else
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v.madd_cmp := '0';
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if new_exp + 1 >= r.b.exponent then
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v.madd_cmp := '1';
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end if;
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v.state := DO_FMADD;
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end if;
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when ADD_SHIFT =>
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opsel_r <= RES_SHIFT;
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v.x := s_nz;
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set_x := '1';
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longmask := '0';
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v.state := ADD_2;
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@@ -1545,6 +1679,78 @@ begin
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v.state := FINISH;
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end if;
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when FMADD_1 =>
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-- Addend is bigger here
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v.result_sign := not (r.b.negative xor r.insn(1) xor r.insn(2));
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-- note v.shift is at most -2 here
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v.shift := r.result_exp - r.b.exponent;
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opsel_r <= RES_MULT;
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opsel_s <= S_MULT;
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set_s := '1';
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f_to_multiply.valid <= r.first;
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if multiply_to_f.valid = '1' then
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v.state := ADD_SHIFT;
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end if;
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when FMADD_2 =>
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-- Product is potentially bigger here
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set_s := '1';
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opsel_s <= S_SHIFT;
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v.shift := r.shift - to_signed(64, EXP_BITS);
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v.state := FMADD_3;
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when FMADD_3 =>
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opsel_r <= RES_SHIFT;
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v.first := '1';
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v.state := FMADD_4;
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when FMADD_4 =>
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msel_add <= MULADD_RS;
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f_to_multiply.valid <= r.first;
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msel_inv <= r.is_subtract;
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opsel_r <= RES_MULT;
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opsel_s <= S_MULT;
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set_s := '1';
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v.shift := to_signed(56, EXP_BITS);
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||||
if multiply_to_f.valid = '1' then
|
||||
if multiply_to_f.result(121) = '1' then
|
||||
v.state := FMADD_5;
|
||||
else
|
||||
v.state := FMADD_6;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when FMADD_5 =>
|
||||
-- negate R:S:X
|
||||
v.result_sign := not r.result_sign;
|
||||
opsel_ainv <= '1';
|
||||
carry_in <= not (s_nz or r.x);
|
||||
opsel_s <= S_NEG;
|
||||
set_s := '1';
|
||||
v.shift := to_signed(56, EXP_BITS);
|
||||
v.state := FMADD_6;
|
||||
|
||||
when FMADD_6 =>
|
||||
if (r.r(56) or r_hi_nz or r_lo_nz or r.r(1) or r.r(0)) = '0' then
|
||||
if s_nz = '0' then
|
||||
-- must be a subtraction, and r.x must be zero
|
||||
v.result_class := ZERO;
|
||||
v.result_sign := r.round_mode(1) and r.round_mode(0);
|
||||
arith_done := '1';
|
||||
else
|
||||
-- R is all zeroes but there are non-zero bits in S
|
||||
-- so shift them into R and set S to 0
|
||||
opsel_r <= RES_SHIFT;
|
||||
set_s := '1';
|
||||
-- stay in state FMADD_6
|
||||
end if;
|
||||
elsif r.r(56 downto 54) = "001" then
|
||||
v.state := FINISH;
|
||||
else
|
||||
renormalize := '1';
|
||||
v.state := NORMALIZE;
|
||||
end if;
|
||||
|
||||
when LOOKUP =>
|
||||
opsel_a <= AIN_B;
|
||||
-- wait one cycle for inverse_table[B] lookup
|
||||
@@ -2097,6 +2303,9 @@ begin
|
||||
when MULADD_A =>
|
||||
-- addend is A in 16.112 format
|
||||
maddend(121 downto 58) := r.a.mantissa;
|
||||
when MULADD_RS =>
|
||||
-- addend is concatenation of R and S in 16.112 format
|
||||
maddend := "000000" & r.r & r.s & "00";
|
||||
when others =>
|
||||
end case;
|
||||
if msel_inv = '1' then
|
||||
@@ -2167,7 +2376,7 @@ begin
|
||||
end if;
|
||||
in_b <= in_b0;
|
||||
if r.shift >= to_signed(-64, EXP_BITS) and r.shift <= to_signed(63, EXP_BITS) then
|
||||
shift_res := shifter_64(r.r & shiftin & 55x"00000000000000",
|
||||
shift_res := shifter_64(r.r & (shiftin or r.s(55)) & r.s(54 downto 0),
|
||||
std_ulogic_vector(r.shift(6 downto 0)));
|
||||
else
|
||||
shift_res := (others => '0');
|
||||
@@ -2230,6 +2439,21 @@ begin
|
||||
result <= misc;
|
||||
end case;
|
||||
v.r := result;
|
||||
if set_s = '1' then
|
||||
case opsel_s is
|
||||
when S_NEG =>
|
||||
v.s := std_ulogic_vector(unsigned(not r.s) + (not r.x));
|
||||
when S_MULT =>
|
||||
v.s := multiply_to_f.result(57 downto 2);
|
||||
when S_SHIFT =>
|
||||
v.s := shift_res(63 downto 8);
|
||||
if shift_res(7 downto 0) /= x"00" then
|
||||
v.x := '1';
|
||||
end if;
|
||||
when others =>
|
||||
v.s := (others => '0');
|
||||
end case;
|
||||
end if;
|
||||
|
||||
if set_a = '1' then
|
||||
v.a.exponent := new_exp;
|
||||
|
||||
@@ -1338,6 +1338,76 @@ int fpu_test_22(void)
|
||||
return trapit(0, test22);
|
||||
}
|
||||
|
||||
struct fmavals {
|
||||
unsigned long ra;
|
||||
unsigned long rc;
|
||||
unsigned long rb;
|
||||
unsigned long fma;
|
||||
unsigned long fms;
|
||||
unsigned long nfma;
|
||||
unsigned long nfms;
|
||||
} fmavals[] = {
|
||||
{ 0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
|
||||
0x0000000000000000, 0x0000000000000000, 0x8000000000000000, 0x8000000000000000 },
|
||||
{ 0x0000000000000000, 0x7ffc000000000000, 0x0000000000000000,
|
||||
0x7ffc000000000000, 0x7ffc000000000000, 0x7ffc000000000000, 0x7ffc000000000000 },
|
||||
{ 0x0000000000000000, 0x7ffc000000000000, 0x7ffb000000000000,
|
||||
0x7ffb000000000000, 0x7ffb000000000000, 0x7ffb000000000000, 0x7ffb000000000000 },
|
||||
{ 0x7ffa000000000000, 0x7ffc000000000000, 0x7ffb000000000000,
|
||||
0x7ffa000000000000, 0x7ffa000000000000, 0x7ffa000000000000, 0x7ffa000000000000 },
|
||||
{ 0x3ff0000000000000, 0x8000000000000000, 0x678123456789abcd,
|
||||
0x678123456789abcd, 0xe78123456789abcd, 0xe78123456789abcd, 0x678123456789abcd },
|
||||
{ 0x3ff0000000000000, 0xbff0000000000000, 0x678123456789abcd,
|
||||
0x678123456789abcd, 0xe78123456789abcd, 0xe78123456789abcd, 0x678123456789abcd },
|
||||
{ 0x7ff0000000000000, 0xbff0000000000000, 0x678123456789abcd,
|
||||
0xfff0000000000000, 0xfff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000 },
|
||||
{ 0x7ff0000000000000, 0x0000000000000000, 0x678123456789abcd,
|
||||
0x7ff8000000000000, 0x7ff8000000000000, 0x7ff8000000000000, 0x7ff8000000000000 },
|
||||
{ 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000020000000,
|
||||
0x4000000010000000, 0xbe80000000000000, 0xc000000010000000, 0x3e80000000000000 },
|
||||
{ 0x3ff0000000000001, 0x3ff0000000000001, 0x3ff0000000000000,
|
||||
0x4000000000000001, 0x3cc0000000000000, 0xc000000000000001, 0xbcc0000000000000 },
|
||||
{ 0x3ff0000000000003, 0x3ff0000000000002, 0x3ff0000000000000,
|
||||
0x4000000000000002, 0x3cd4000000000002, 0xc000000000000002, 0xbcd4000000000002 },
|
||||
{ 0x3006a09e667f3bcc, 0x4006a09e667f3bcd, 0xb020000000000000,
|
||||
0xaca765753908cd20, 0x3030000000000000, 0x2ca765753908cd20, 0xb030000000000000 },
|
||||
{ 0x3006a09e667f3bcd, 0x4006a09e667f3bcd, 0xb020000000000000,
|
||||
0x2cd3b3efbf5e2229, 0x3030000000000000, 0xacd3b3efbf5e2229, 0xb030000000000000 },
|
||||
{ 0x3006a09e667f3bcc, 0x4006a09e667f3bcd, 0xb060003450000000,
|
||||
0xb05e0068a0000000, 0x3061003450000000, 0x305e0068a0000000, 0xb061003450000000 },
|
||||
};
|
||||
|
||||
int test23(long arg)
|
||||
{
|
||||
long i;
|
||||
unsigned long results[4];
|
||||
struct fmavals *vp = fmavals;
|
||||
|
||||
set_fpscr(FPS_RN_NEAR);
|
||||
for (i = 0; i < sizeof(fmavals) / sizeof(fmavals[0]); ++i, ++vp) {
|
||||
asm("lfd 6,0(%0); lfd 7,8(%0); lfd 8,16(%0); fmadd 0,6,7,8; stfd 0,0(%1)"
|
||||
: : "b" (&vp->ra), "b" (results) : "memory");
|
||||
asm("fmsub 1,6,7,8; fnmadd 2,6,7,8; fnmsub 3,6,7,8; stfd 1,8(%0); stfd 2,16(%0); stfd 3,24(%0)"
|
||||
: : "b" (results) : "memory");
|
||||
if (results[0] != vp->fma || results[1] != vp->fms ||
|
||||
results[2] != vp->nfma || results[3] != vp->nfms) {
|
||||
print_hex(i, 2, " ");
|
||||
print_hex(results[0], 16, " ");
|
||||
print_hex(results[1], 16, " ");
|
||||
print_hex(results[2], 16, " ");
|
||||
print_hex(results[3], 16, "\r\n");
|
||||
return i + 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fpu_test_23(void)
|
||||
{
|
||||
enable_fp();
|
||||
return trapit(0, test23);
|
||||
}
|
||||
|
||||
int fail = 0;
|
||||
|
||||
void do_test(int num, int (*test)(void))
|
||||
@@ -1385,6 +1455,7 @@ int main(void)
|
||||
do_test(20, fpu_test_20);
|
||||
do_test(21, fpu_test_21);
|
||||
do_test(22, fpu_test_22);
|
||||
do_test(23, fpu_test_23);
|
||||
|
||||
return fail;
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -20,3 +20,4 @@ test 19:PASS
|
||||
test 20:PASS
|
||||
test 21:PASS
|
||||
test 22:PASS
|
||||
test 23:PASS
|
||||
|
||||
Reference in New Issue
Block a user