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FPU: Make sure FR and FI in FPSCR get reset on special-case arith instructions

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Arithmetic instructions where the result is determined without doing any
actual computation (i.e. the input(s) are NaNs, infinities, zeroes etc.)
weren't resetting FR and FI properly.  This combines the two blocks that
handle the r.cycle_1_ar = 1 case to fix it.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras 2025-11-18 22:42:37 +00:00
parent 0b3df8ab00
commit e60840eabc
1 changed files with 3 additions and 6 deletions
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9
fpu.vhdl
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@ -1354,12 +1354,6 @@ begin
rsgn_op := RSGN_NOP;
rcls_op <= RCLS_NOP;
if r.cycle_1_ar = '1' then
v.fpscr(FPSCR_FR) := '0';
v.fpscr(FPSCR_FI) := '0';
v.result_class := FINITE;
end if;
case r.state is
when IDLE =>
v.invalid := '0';
@ -3077,6 +3071,9 @@ begin
-- Handle exceptions and special cases for arithmetic operations
if r.cycle_1_ar = '1' then
v.fpscr := r.fpscr or scinfo.new_fpscr;
v.fpscr(FPSCR_FR) := '0';
v.fpscr(FPSCR_FI) := '0';
v.result_class := FINITE;
invalid := scinfo.invalid;
zero_divide := scinfo.zero_divide;
qnan_result := scinfo.qnan_result;