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fpga/bram: Generate stall signal

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This doesn't yet pipeline the block RAM, just generate a valid stall
signal so it's compatible with a pipelined master

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2019-10-19 21:22:33 +11:00
parent 37acb35773
commit e638c3e8ae
1 changed files with 2 additions and 1 deletions
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fpga/mw_soc_memory.vhdl
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@@ -65,7 +65,8 @@ begin
wb_adr_in <= wishbone_in.adr(log2(MEMORY_SIZE) - 1 downto 0);
wishbone_out.ack <= read_ack and wishbone_in.stb;
wishbone_out.ack <= read_ack and wishbone_in.cyc and wishbone_in.stb;
wishbone_out.stall <= '0' when wishbone_in.cyc = '0' else not wishbone_out.ack;
memory_0: process(clk)
begin