dcache: Fix bug in store hit after dcbz case

This fixes a bug where a store that hits in the dcache immediately
following a dcbz has its write to the cache RAM suppressed (but not
its write to memory).  If a load to the same location comes along
before the cache line gets replaced, the load will return incorrect
data.

Fixes: 4db1676ef8 ("dcache: Don't assert on dcbz cache hit")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

dcache.vhdl

@@ -980,7 +980,7 @@ begin
 		do_write <= '1';
 	    end if;
 	    if req_op = OP_STORE_HIT and req_hit_way = i and cancel_store = '0' and
-                r1.req.dcbz = '0' then
+                r0.req.dcbz = '0' then
 		assert not reloading report "Store hit while in state:" &
 		    state_t'image(r1.state)
 		    severity FAILURE;