core: Double the dcache and icache sizes

This makes the dcache and icache both be 8kB.  This still only uses
one BRAM per way per cache on the Artix-7, since the BRAMs were only
half-used previously.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

core.vhdl

@@ -195,7 +195,7 @@ begin
         generic map(
             SIM => SIM,
             LINE_SIZE => 64,
-            NUM_LINES => 32,
+            NUM_LINES => 64,
 	    NUM_WAYS => 2
             )
         port map(
@@ -335,7 +335,7 @@ begin
     dcache_0: entity work.dcache
         generic map(
             LINE_SIZE => 64,
-            NUM_LINES => 32,
+            NUM_LINES => 64,
 	    NUM_WAYS => 2
             )
         port map (