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soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding

Browse Source 
This makes the control bus currently going out of "soc" towards
litedram more generic for external IO devices added by the
top-level rather than inside the SoC proper.

This is mostly renaming of signals and a small change on how the
address decoder operates, using a separate "cascaded" decode for
the external IOs.

We make the region 0xc8nn_nnnn be the "external IO" region for
now.

This will make it easier / cleaner to add more external devices.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2020-06-13 22:04:45 +10:00
parent bf7def5503
commit f9f18906a3
8 changed files with 220 additions and 225 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
core_dram_tb.vhdl
View File

@@ -26,10 +26,10 @@ architecture behave of core_dram_tb is
-- Sim DRAM
signal wb_dram_in : wishbone_master_out;
signal wb_dram_out : wishbone_slave_out;
signal wb_dram_ctrl_in : wb_io_master_out;
signal wb_dram_ctrl_out : wb_io_slave_out;
signal wb_dram_is_csr : std_ulogic;
signal wb_dram_is_init : std_ulogic;
signal wb_ext_io_in : wb_io_master_out;
signal wb_ext_io_out : wb_io_slave_out;
signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic;
signal core_alt_reset : std_ulogic;
-- SPI
@@ -74,10 +74,10 @@ begin
system_clk => system_clk,
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_dram_ctrl_in => wb_dram_ctrl_in,
wb_dram_ctrl_out => wb_dram_ctrl_out,
wb_dram_is_csr => wb_dram_is_csr,
wb_dram_is_init => wb_dram_is_init,
wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init,
spi_flash_sck => spi_sck,
spi_flash_cs_n => spi_cs_n,
spi_flash_sdat_o => spi_sdat_o,
@@ -124,38 +124,18 @@ begin
PAYLOAD_SIZE => ROM_SIZE
)
port map(
clk_in => clk,
clk_in => clk,
rst => rst,
system_clk => system_clk,
system_reset => soc_rst,
core_alt_reset => core_alt_reset,
pll_locked => open,
system_clk => system_clk,
system_reset => soc_rst,
core_alt_reset => core_alt_reset,
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_ctrl_in => wb_dram_ctrl_in,
wb_ctrl_out => wb_dram_ctrl_out,
wb_ctrl_is_csr => wb_dram_is_csr,
wb_ctrl_is_init => wb_dram_is_init,
init_done => open,
init_error => open,
ddram_a => open,
ddram_ba => open,
ddram_ras_n => open,
ddram_cas_n => open,
ddram_we_n => open,
ddram_cs_n => open,
ddram_dm => open,
ddram_dq => open,
ddram_dqs_p => open,
ddram_dqs_n => open,
ddram_clk_p => open,
ddram_clk_n => open,
ddram_cke => open,
ddram_odt => open,
ddram_reset_n => open
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_ctrl_in => wb_ext_io_in,
wb_ctrl_out => wb_ext_io_out,
wb_ctrl_is_csr => wb_ext_is_dram_csr,
wb_ctrl_is_init => wb_ext_is_dram_init
);
clk_process: process

32
fpga/top-arty.vhdl
View File

@@ -77,10 +77,12 @@ architecture behaviour of toplevel is
signal wb_dram_out : wishbone_slave_out;
-- DRAM control wishbone connection
signal wb_dram_ctrl_in : wb_io_master_out;
signal wb_dram_ctrl_out : wb_io_slave_out;
signal wb_dram_is_csr : std_ulogic;
signal wb_dram_is_init : std_ulogic;
signal wb_ext_io_in : wb_io_master_out;
signal wb_ext_io_out : wb_io_slave_out;
signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic;
signal wb_ext_is_eth : std_ulogic;
-- Control/status
signal core_alt_reset : std_ulogic;
@@ -157,13 +159,13 @@ begin
spi_flash_sdat_i => spi_sdat_i,
-- DRAM wishbone
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_dram_ctrl_in => wb_dram_ctrl_in,
wb_dram_ctrl_out => wb_dram_ctrl_out,
wb_dram_is_csr => wb_dram_is_csr,
wb_dram_is_init => wb_dram_is_init,
alt_reset => core_alt_reset
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init,
alt_reset => core_alt_reset
);
-- SPI Flash
@@ -291,10 +293,10 @@ begin
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_ctrl_in => wb_dram_ctrl_in,
wb_ctrl_out => wb_dram_ctrl_out,
wb_ctrl_is_csr => wb_dram_is_csr,
wb_ctrl_is_init => wb_dram_is_init,
wb_ctrl_in => wb_ext_io_in,
wb_ctrl_out => wb_ext_io_out,
wb_ctrl_is_csr => wb_ext_is_dram_csr,
wb_ctrl_is_init => wb_ext_is_dram_init,
init_done => dram_init_done,
init_error => dram_init_error,

30
fpga/top-nexys-video.vhdl
View File

@@ -73,10 +73,10 @@ architecture behaviour of toplevel is
signal wb_dram_out : wishbone_slave_out;
-- DRAM control wishbone connection
signal wb_dram_ctrl_in : wb_io_master_out;
signal wb_dram_ctrl_out : wb_io_slave_out;
signal wb_dram_is_csr : std_ulogic;
signal wb_dram_is_init : std_ulogic;
signal wb_ext_io_in : wb_io_master_out;
signal wb_ext_io_out : wb_io_slave_out;
signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic;
-- Control/status
signal core_alt_reset : std_ulogic;
@@ -145,13 +145,13 @@ begin
spi_flash_sdat_i => spi_sdat_i,
-- DRAM wishbone
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_dram_ctrl_in => wb_dram_ctrl_in,
wb_dram_ctrl_out => wb_dram_ctrl_out,
wb_dram_is_csr => wb_dram_is_csr,
wb_dram_is_init => wb_dram_is_init,
alt_reset => core_alt_reset
wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out,
wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_dram_is_csr,
wb_ext_is_dram_init => wb_dram_is_init,
alt_reset => core_alt_reset
);
-- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
@@ -266,10 +266,10 @@ begin
wb_in => wb_dram_in,
wb_out => wb_dram_out,
wb_ctrl_in => wb_dram_ctrl_in,
wb_ctrl_out => wb_dram_ctrl_out,
wb_ctrl_is_csr => wb_dram_is_csr,
wb_ctrl_is_init => wb_dram_is_init,
wb_ctrl_in => wb_ext_io_in,
wb_ctrl_out => wb_ext_io_out,
wb_ctrl_is_csr => wb_ext_is_dram_csr,
wb_ctrl_is_init => wb_ext_is_dram_init,
init_done => dram_init_done,
init_error => dram_init_error,

2
include/microwatt_soc.h
View File

@@ -13,7 +13,7 @@
#define UART_BASE 0xc0002000 /* UART */
#define XICS_BASE 0xc0004000 /* Interrupt controller */
#define SPI_FCTRL_BASE 0xc0006000 /* SPI flash controller registers */
#define DRAM_CTRL_BASE 0xc0100000 /* LiteDRAM control registers */
#define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */
#define SPI_FLASH_BASE 0xf0000000 /* SPI Flash memory map */
#define DRAM_INIT_BASE 0xff000000 /* Internal DRAM init firmware */

102
litedram/generated/arty/litedram_core.init
View File

@@ -724,9 +724,9 @@ a12100a660000000
4bfff9a938637cb0
000000004bfffd78
0000088003000000
612908043d20c010
612908043d20c800
7c0004ac79290020
3d40c0107c604f2a
3d40c8007c604f2a
614a080839200001
7c0004ac794a0020
4e8000207d20572a
@@ -736,29 +736,29 @@ a12100a660000000
600000007d2903a6
4e8000204200fffc
0000000000000000
3d20c01000000000
3d20c80000000000
6129001439400001
792900207d431830
7c604f2a7c0004ac
610800183d00c010
610800183d00c800
7c0004ac79080020
394000007d40472a
7d404f2a7c0004ac
000000004e800020
0000000000000000
394000013d20c010
394000013d20c800
7d43183061290014
7c0004ac79290020
3d00c0107c604f2a
3d00c8007c604f2a
790800206108001c
7d40472a7c0004ac
7c0004ac39400000
4e8000207d404f2a
0000000000000000
3d40c01000000000
3d40c80000000000
614a083439200025
7c0004ac794a0020
3d40c0107d20572a
3d40c8007d20572a
614a083839200001
7c0004ac794a0020
4e8000207d20572a
@@ -796,38 +796,38 @@ a12100a660000000
38c600017ce831ae
394affff4200ffe0
794a002139080004
3d20c0104082ffc4
3d20c8004082ffc4
6129080c3be00000
7c0004ac79290020
3d20c0107fe04f2a
3d20c8007fe04f2a
7929002061290810
7fe04f2a7c0004ac
4bfffd8d38600009
4bfffdc13860000f
7fa4eb783c60c010
7fa4eb783c60c800
7863002060630814
3c60c0104bfffead
3c60c8004bfffead
6063082c38810064
4bfffe9978630020
388100683c60c010
388100683c60c800
7863002060630844
3c60c0104bfffe85
3c60c8004bfffe85
6063085c3881006c
4bfffe7178630020
612908543d20c010
612908543d20c800
7c0004ac79290020
3d20c0107fe04f2a
3d20c8007fe04f2a
7929002061290858
7fe04f2a7c0004ac
392000173d40c010
392000173d40c800
794a0020614a084c
7d20572a7c0004ac
392000013d40c010
392000013d40c800
794a0020614a0850
7d20572a7c0004ac
6129083c3d20c010
6129083c3d20c800
7c0004ac79290020
3d20c0107fe04f2a
3d20c8007fe04f2a
7929002061290840
7fe04f2a7c0004ac
22de00017fc3f378
@@ -880,10 +880,10 @@ a12100a660000000
600000004bfff4cd
3be000007fc3f378
7f9fe8004bfffb8d
3d40c010419c0070
3d40c800419c0070
614a080c39200000
7c0004ac794a0020
3d40c0107d20572a
3d40c8007d20572a
794a0020614a0810
7d20572a7c0004ac
4bfffaed3860000b
@@ -899,7 +899,7 @@ a12100a660000000
000000004bffff7c
00000b8001000000
384299e03c4c0001
3d40c0107c0802a6
3d40c8007c0802a6
3920000e614a0800
f8010010794a0020
7c0004acf821ffa1
@@ -910,7 +910,7 @@ f8010010794a0020
000000004e800020
0000008001000000
384299883c4c0001
3d40c0107c0802a6
3d40c8007c0802a6
39200001614a0800
f8010010794a0020
7c0004acf821ffa1
@@ -1016,11 +1016,11 @@ f92a0000794a1f24
3c4c000100000380
7c0802a638429644
f821fec1480010f5
3bc000013fe0c010
3bc000013fe0c800
7bff002063ff0014
386000004bfffc49
7c0004ac4bfff72d
3f80c0107fc0ff2a
3f80c8007fc0ff2a
7b9c0020639c0020
7fc0e72a7c0004ac
7c0004ac3ba00000
@@ -1040,7 +1040,7 @@ f92100983ae10063
39ef7fa83a107f28
3a527f6839ce7fb0
3b20000139210064
3ea0c0103e80c010
3ea0c8003e80c800
39210068f9210088
6294080c7f39f830
7b33002062b50810
@@ -1049,9 +1049,9 @@ f92100903bc00000
7ab500207a940020
7fbeeb7848000054
419e029c2f9d000f
612900143d20c010
612900143d20c800
7c0004ac79290020
3d00c0107e604f2a
3d00c8007e604f2a
6108002439400001
7c0004ac79080020
394000007d40472a
@@ -1073,31 +1073,31 @@ f92100903bc00000
7c0004ac7f60a72a
386000097f60af2a
3860000f4bfff521
3c60c0104bfff555
3c60c8004bfff555
606308147f44d378
4bfff64178630020
3c60c010e8810088
3c60c800e8810088
786300206063082c
e88100904bfff62d
606308443c60c010
606308443c60c800
4bfff61978630020
3881006c3c60c010
3881006c3c60c800
786300206063085c
3d20c0104bfff605
3d20c8004bfff605
7929002061290854
7f604f2a7c0004ac
612908583d20c010
612908583d20c800
7c0004ac79290020
3d40c0107f604f2a
3d40c8007f604f2a
614a084c39200017
7c0004ac794a0020
3d40c0107d20572a
3d40c8007d20572a
614a085039200001
7c0004ac794a0020
3d20c0107d20572a
3d20c8007d20572a
792900206129083c
7f604f2a7c0004ac
612908403d20c010
612908403d20c800
7c0004ac79290020
e86100987f604f2a
7fe4fb787fa5eb78
@@ -1135,14 +1135,14 @@ f94100a0e8810080
7fc5f3783c62ffff
38637fb87fe4fb78
600000004bffecc5
612900143d20c010
612900143d20c800
7c0004ac79290020
3d00c0107f204f2a
3d00c8007f204f2a
6108002039400001
7c0004ac79080020
394000007d40472a
7d404f2a7c0004ac
3d00c0107bde0020
3d00c8007bde0020
6108002438de0001
394000017cc903a6
38e0000079080020
@@ -1162,19 +1162,19 @@ f94100a0e8810080
384291b83c4c0001
3c62ffff7c0802a6
48000c9138637f70
3f60c010f821ff71
3f60c800f821ff71
637b10003be00000
4bffebd17b7b0020
7c0004ac60000000
3f40c0107fe0df2a
3f40c8007fe0df2a
7b5a0020635a1004
7fe0d72a7c0004ac
4bfff78d3fa0c010
4bfff78d3fa0c800
7bbd002063bd080c
7fe0ef2a7c0004ac
63de08103fc0c010
63de08103fc0c800
7c0004ac7bde0020
3f80c0107fe0f72a
3f80c8007fe0f72a
639c08003920000c
7c0004ac7b9c0020
386000007d20e72a
@@ -1699,10 +1699,10 @@ e8010010ebc1fff0
000000000000002d
30252d2b64323025
0000000000006432
00000000c0100818
00000000c0100830
00000000c0100848
00000000c0100860
00000000c8000818
00000000c8000830
00000000c8000848
00000000c8000860
6f6e204d41524453
207265646e752077
6572617764726168

102
litedram/generated/nexys-video/litedram_core.init
View File

@@ -724,9 +724,9 @@ a12100a660000000
4bfff9a938637cb0
000000004bfffd78
0000088003000000
612908043d20c010
612908043d20c800
7c0004ac79290020
3d40c0107c604f2a
3d40c8007c604f2a
614a080839200001
7c0004ac794a0020
4e8000207d20572a
@@ -736,29 +736,29 @@ a12100a660000000
600000007d2903a6
4e8000204200fffc
0000000000000000
3d20c01000000000
3d20c80000000000
6129001439400001
792900207d431830
7c604f2a7c0004ac
610800183d00c010
610800183d00c800
7c0004ac79080020
394000007d40472a
7d404f2a7c0004ac
000000004e800020
0000000000000000
394000013d20c010
394000013d20c800
7d43183061290014
7c0004ac79290020
3d00c0107c604f2a
3d00c8007c604f2a
790800206108001c
7d40472a7c0004ac
7c0004ac39400000
4e8000207d404f2a
0000000000000000
3d40c01000000000
3d40c80000000000
614a083439200025
7c0004ac794a0020
3d40c0107d20572a
3d40c8007d20572a
614a083839200001
7c0004ac794a0020
4e8000207d20572a
@@ -796,38 +796,38 @@ a12100a660000000
38c600017ce831ae
394affff4200ffe0
794a002139080004
3d20c0104082ffc4
3d20c8004082ffc4
6129080c3be00000
7c0004ac79290020
3d20c0107fe04f2a
3d20c8007fe04f2a
7929002061290810
7fe04f2a7c0004ac
4bfffd8d38600009
4bfffdc13860000f
7fa4eb783c60c010
7fa4eb783c60c800
7863002060630814
3c60c0104bfffead
3c60c8004bfffead
6063082c38810064
4bfffe9978630020
388100683c60c010
388100683c60c800
7863002060630844
3c60c0104bfffe85
3c60c8004bfffe85
6063085c3881006c
4bfffe7178630020
612908543d20c010
612908543d20c800
7c0004ac79290020
3d20c0107fe04f2a
3d20c8007fe04f2a
7929002061290858
7fe04f2a7c0004ac
392000173d40c010
392000173d40c800
794a0020614a084c
7d20572a7c0004ac
392000013d40c010
392000013d40c800
794a0020614a0850
7d20572a7c0004ac
6129083c3d20c010
6129083c3d20c800
7c0004ac79290020
3d20c0107fe04f2a
3d20c8007fe04f2a
7929002061290840
7fe04f2a7c0004ac
22de00017fc3f378
@@ -880,10 +880,10 @@ a12100a660000000
600000004bfff4cd
3be000007fc3f378
7f9fe8004bfffb8d
3d40c010419c0070
3d40c800419c0070
614a080c39200000
7c0004ac794a0020
3d40c0107d20572a
3d40c8007d20572a
794a0020614a0810
7d20572a7c0004ac
4bfffaed3860000b
@@ -899,7 +899,7 @@ a12100a660000000
000000004bffff7c
00000b8001000000
384299e03c4c0001
3d40c0107c0802a6
3d40c8007c0802a6
3920000e614a0800
f8010010794a0020
7c0004acf821ffa1
@@ -910,7 +910,7 @@ f8010010794a0020
000000004e800020
0000008001000000
384299883c4c0001
3d40c0107c0802a6
3d40c8007c0802a6
39200001614a0800
f8010010794a0020
7c0004acf821ffa1
@@ -1016,11 +1016,11 @@ f92a0000794a1f24
3c4c000100000380
7c0802a638429644
f821fec1480010f5
3bc000013fe0c010
3bc000013fe0c800
7bff002063ff0014
386000004bfffc49
7c0004ac4bfff72d
3f80c0107fc0ff2a
3f80c8007fc0ff2a
7b9c0020639c0020
7fc0e72a7c0004ac
7c0004ac3ba00000
@@ -1040,7 +1040,7 @@ f92100983ae10063
39ef7fa83a107f28
3a527f6839ce7fb0
3b20000139210064
3ea0c0103e80c010
3ea0c8003e80c800
39210068f9210088
6294080c7f39f830
7b33002062b50810
@@ -1049,9 +1049,9 @@ f92100903bc00000
7ab500207a940020
7fbeeb7848000054
419e029c2f9d000f
612900143d20c010
612900143d20c800
7c0004ac79290020
3d00c0107e604f2a
3d00c8007e604f2a
6108002439400001
7c0004ac79080020
394000007d40472a
@@ -1073,31 +1073,31 @@ f92100903bc00000
7c0004ac7f60a72a
386000097f60af2a
3860000f4bfff521
3c60c0104bfff555
3c60c8004bfff555
606308147f44d378
4bfff64178630020
3c60c010e8810088
3c60c800e8810088
786300206063082c
e88100904bfff62d
606308443c60c010
606308443c60c800
4bfff61978630020
3881006c3c60c010
3881006c3c60c800
786300206063085c
3d20c0104bfff605
3d20c8004bfff605
7929002061290854
7f604f2a7c0004ac
612908583d20c010
612908583d20c800
7c0004ac79290020
3d40c0107f604f2a
3d40c8007f604f2a
614a084c39200017
7c0004ac794a0020
3d40c0107d20572a
3d40c8007d20572a
614a085039200001
7c0004ac794a0020
3d20c0107d20572a
3d20c8007d20572a
792900206129083c
7f604f2a7c0004ac
612908403d20c010
612908403d20c800
7c0004ac79290020
e86100987f604f2a
7fe4fb787fa5eb78
@@ -1135,14 +1135,14 @@ f94100a0e8810080
7fc5f3783c62ffff
38637fb87fe4fb78
600000004bffecc5
612900143d20c010
612900143d20c800
7c0004ac79290020
3d00c0107f204f2a
3d00c8007f204f2a
6108002039400001
7c0004ac79080020
394000007d40472a
7d404f2a7c0004ac
3d00c0107bde0020
3d00c8007bde0020
6108002438de0001
394000017cc903a6
38e0000079080020
@@ -1162,19 +1162,19 @@ f94100a0e8810080
384291b83c4c0001
3c62ffff7c0802a6
48000c9138637f70
3f60c010f821ff71
3f60c800f821ff71
637b10003be00000
4bffebd17b7b0020
7c0004ac60000000
3f40c0107fe0df2a
3f40c8007fe0df2a
7b5a0020635a1004
7fe0d72a7c0004ac
4bfff78d3fa0c010
4bfff78d3fa0c800
7bbd002063bd080c
7fe0ef2a7c0004ac
63de08103fc0c010
63de08103fc0c800
7c0004ac7bde0020
3f80c0107fe0f72a
3f80c8007fe0f72a
639c08003920000c
7c0004ac7b9c0020
386000007d20e72a
@@ -1699,10 +1699,10 @@ e8010010ebc1fff0
000000000000002d
30252d2b64323025
0000000000006432
00000000c0100818
00000000c0100830
00000000c0100848
00000000c0100860
00000000c8000818
00000000c8000830
00000000c8000848
00000000c8000860
6f6e204d41524453
207265646e752077
6572617764726168

18
litedram/generated/sim/litedram_core.init
View File

@@ -724,16 +724,16 @@ a12100a660000000
4bfff9a938637dd0
000000004bfffd78
0000088003000000
612908043d20c010
612908043d20c800
7c0004ac79290020
3d40c0107c604f2a
3d40c8007c604f2a
614a080839200001
7c0004ac794a0020
4e8000207d20572a
0000000000000000
3c4c000100000000
7c0802a638429414
614a08003d40c010
614a08003d40c800
794a00203920000e
f821ffa1f8010010
7d20572a7c0004ac
@@ -744,7 +744,7 @@ e801001038210060
0100000000000000
3c4c000100000080
7c0802a6384293bc
614a08003d40c010
614a08003d40c800
794a002039200001
f821ffa1f8010010
7d20572a7c0004ac
@@ -851,19 +851,19 @@ e801001038210060
384290703c4c0001
600000007c0802a6
48000c6938628048
3f60c010f821ff71
3f60c800f821ff71
637b10003be00000
4bfff5897b7b0020
7c0004ac60000000
3f40c0107fe0df2a
3f40c8007fe0df2a
7b5a0020635a1004
7fe0d72a7c0004ac
4bfffc113fa0c010
4bfffc113fa0c800
7bbd002063bd080c
7fe0ef2a7c0004ac
63de08103fc0c010
63de08103fc0c800
7c0004ac7bde0020
3d20c0107fe0f72a
3d20c8007fe0f72a
612908003940000c
7c0004ac79290020
7c0004ac7d404f2a

103
soc.vhdl
View File

@@ -22,9 +22,17 @@ use work.wishbone_types.all;
-- 0xc0002000: UART0
-- 0xc0004000: XICS ICP
-- 0xc0006000: SPI Flash controller
-- 0xc0100000: LiteDRAM control (CSRs)
-- 0xc8nnnnnn: External IO bus
-- 0xf0000000: Flash "ROM" mapping
-- 0xff000000: DRAM init code (if any) or flash ROM
-- 0xff000000: DRAM init code (if any) or flash ROM (**)
-- External IO bus:
-- 0xc8000000: LiteDRAM control (CSRs)
-- (**) DRAM init code is currently special and goes to the external
-- IO bus, this will be fixed when it's moved out of litedram and
-- into the main SoC once we have a common "firmware".
entity soc is
generic (
@@ -46,13 +54,15 @@ entity soc is
rst : in std_ulogic;
system_clk : in std_ulogic;
-- DRAM controller signals
-- "Large" (64-bit) DRAM wishbone
wb_dram_in : out wishbone_master_out;
wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
wb_dram_ctrl_in : out wb_io_master_out;
wb_dram_ctrl_out : in wb_io_slave_out := wb_io_slave_out_init;
wb_dram_is_csr : out std_ulogic;
wb_dram_is_init : out std_ulogic;
-- "Small" (32-bit) external IO wishbone
wb_ext_io_in : out wb_io_master_out;
wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
wb_ext_is_dram_csr : out std_ulogic;
wb_ext_is_dram_init : out std_ulogic;
-- UART0 signals:
uart0_txd : out std_ulogic;
@@ -153,15 +163,14 @@ architecture behaviour of soc is
signal rst_wbdb : std_ulogic := '1';
signal alt_reset_d : std_ulogic;
-- IO branch split:
type slave_io_type is (SLAVE_IO_SYSCON,
SLAVE_IO_UART,
SLAVE_IO_DRAM_INIT,
SLAVE_IO_DRAM_CSR,
SLAVE_IO_ICP_0,
SLAVE_IO_SPI_FLASH_REG,
SLAVE_IO_SPI_FLASH_MAP,
SLAVE_IO_NONE);
-- IO branch split:
type slave_io_type is (SLAVE_IO_SYSCON,
SLAVE_IO_UART,
SLAVE_IO_ICP_0,
SLAVE_IO_SPI_FLASH_REG,
SLAVE_IO_SPI_FLASH_MAP,
SLAVE_IO_EXTERNAL,
SLAVE_IO_NONE);
signal slave_io_dbg : slave_io_type;
begin
@@ -426,25 +435,26 @@ begin
-- IO wishbone slave intercon.
--
slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out,
wb_dram_ctrl_out, wb_xics0_out, wb_spiflash_out)
wb_ext_io_out, wb_xics0_out, wb_spiflash_out)
variable slave_io : slave_io_type;
variable match : std_ulogic_vector(31 downto 12);
variable ext_valid : boolean;
begin
-- Simple address decoder.
slave_io := SLAVE_IO_NONE;
match := "11" & wb_sio_out.adr(29 downto 12);
if std_match(match, x"FF---") and HAS_DRAM then
slave_io := SLAVE_IO_DRAM_INIT;
slave_io := SLAVE_IO_EXTERNAL;
elsif std_match(match, x"F----") then
slave_io := SLAVE_IO_SPI_FLASH_MAP;
elsif std_match(match, x"C0000") then
slave_io := SLAVE_IO_SYSCON;
elsif std_match(match, x"C0002") then
slave_io := SLAVE_IO_UART;
elsif std_match(match, x"C01--") then
slave_io := SLAVE_IO_DRAM_CSR;
elsif std_match(match, x"C8---") then
slave_io := SLAVE_IO_EXTERNAL;
elsif std_match(match, x"C0004") then
slave_io := SLAVE_IO_ICP_0;
elsif std_match(match, x"C0006") then
@@ -464,35 +474,41 @@ begin
wb_xics0_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
wb_xics0_in.cyc <= '0';
wb_dram_ctrl_in <= wb_sio_out;
wb_dram_ctrl_in.cyc <= '0';
wb_dram_is_csr <= '0';
wb_dram_is_init <= '0';
wb_ext_io_in <= wb_sio_out;
wb_ext_io_in.cyc <= '0';
wb_syscon_in <= wb_sio_out;
wb_syscon_in.cyc <= '0';
wb_ext_is_dram_csr <= '0';
wb_ext_is_dram_init <= '0';
-- Default response, ack & return all 1's
wb_sio_in.dat <= (others => '1');
wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
wb_sio_in.stall <= '0';
case slave_io is
when SLAVE_IO_DRAM_INIT =>
if HAS_DRAM then
wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
wb_sio_in <= wb_dram_ctrl_out;
else
wb_sio_in.ack <= wb_sio_out.cyc and wb_sio_out.stb;
wb_sio_in.dat <= (others => '1');
wb_sio_in.stall <= '0';
when SLAVE_IO_EXTERNAL =>
-- Ext IO "chip selects"
--
-- DRAM init is special at 0xFF* so we just test the top
-- bit. Everything else is at 0xC8* so we test only bits
-- 23 downto 16.
--
ext_valid := false;
if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
wb_ext_is_dram_init <= '1';
ext_valid := true;
elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
wb_ext_is_dram_csr <= '1';
ext_valid := true;
end if;
wb_dram_is_init <= '1';
when SLAVE_IO_DRAM_CSR =>
if HAS_DRAM then
wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
wb_sio_in <= wb_dram_ctrl_out;
else
wb_sio_in.ack <= wb_sio_out.cyc and wb_sio_out.stb;
wb_sio_in.dat <= (others => '1');
wb_sio_in.stall <= '0';
if ext_valid then
wb_ext_io_in.cyc <= wb_sio_out.cyc;
wb_sio_in <= wb_ext_io_out;
end if;
wb_dram_is_csr <= '1';
when SLAVE_IO_SYSCON =>
wb_syscon_in.cyc <= wb_sio_out.cyc;
wb_sio_in <= wb_syscon_out;
@@ -514,9 +530,6 @@ begin
wb_sio_in <= wb_spiflash_out;
wb_spiflash_is_reg <= '1';
when others =>
wb_sio_in.dat <= (others => '1');
wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
wb_sio_in.stall <= '0';
end case;
end process;