github.com/antonblanchard.microwatt
1
0
Fork 0
mirror of https://github.com/antonblanchard/microwatt.git synced 2026-01-11 23:43:15 +00:00
Code Releases Activity

Reformat sim_console

Browse Source 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2019-09-19 20:28:37 +10:00 committed by Anton Blanchard
parent 28e6d343dc
commit fd9e971b2c
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
sim_console.vhdl
View File

@ -2,29 +2,29 @@ library ieee;
use ieee.std_logic_1164.all;
package sim_console is
procedure sim_console_read (val: out std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_read : procedure is "VHPIDIRECT sim_console_read";
procedure sim_console_read (val: out std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_read : procedure is "VHPIDIRECT sim_console_read";
procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_poll : procedure is "VHPIDIRECT sim_console_poll";
procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_poll : procedure is "VHPIDIRECT sim_console_poll";
procedure sim_console_write (val: std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_write : procedure is "VHPIDIRECT sim_console_write";
procedure sim_console_write (val: std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_write : procedure is "VHPIDIRECT sim_console_write";
end sim_console;
package body sim_console is
procedure sim_console_read (val: out std_ulogic_vector(63 downto 0)) is
begin
assert false report "VHPI" severity failure;
end sim_console_read;
procedure sim_console_read (val: out std_ulogic_vector(63 downto 0)) is
begin
assert false report "VHPI" severity failure;
end sim_console_read;
procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0)) is
begin
assert false report "VHPI" severity failure;
end sim_console_poll;
procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0)) is
begin
assert false report "VHPI" severity failure;
end sim_console_poll;
procedure sim_console_write (val: std_ulogic_vector(63 downto 0)) is
begin
assert false report "VHPI" severity failure;
end sim_console_write;
procedure sim_console_write (val: std_ulogic_vector(63 downto 0)) is
begin
assert false report "VHPI" severity failure;
end sim_console_write;
end sim_console;