Anton Blanchard 3e8a6a8fc2 Add yosys/verilator support ...

Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

2020-05-19 15:18:42 +10:00

1.3 KiB

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