mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-02-09 09:41:23 +00:00
167e37d667
In preparation for adding a TLB to the dcache, this plumbs the insn_type from execute1 through to loadstore1, so that we can have other operations besides loads and stores (e.g. tlbie) going to loadstore1 and thence to the dcache. This also plumbs the unit field of the decode ROM from decode2 through to execute1 to simplify the logic around which ops need to go to loadstore1. The load and store data formatting are now not conditional on the op being OP_LOAD or OP_STORE. This eliminates the inferred latches clocked by each of the bits of r.op that we were getting previously. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
162 lines
5.3 KiB
Makefile
162 lines
5.3 KiB
Makefile
GHDL=ghdl
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GHDLFLAGS=--std=08 -Psim-unisim
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CFLAGS=-O2 -Wall
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# We need a version of GHDL built with either the LLVM or gcc backend.
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# Fedora provides this, but other distros may not. Another option, although
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# rather slow, is to use the Docker image.
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#
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# Uncomment one of these to build with Docker or podman
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#DOCKER=docker
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#DOCKER=podman
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#
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# Uncomment these lines to build with Docker/podman
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#PWD = $(shell pwd)
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#DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
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#GHDL = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
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#CC = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
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all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
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rotator_tb countzero_tb wishbone_bram_tb
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# XXX
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# loadstore_tb fetch_tb
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all: $(all)
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%.o : %.vhdl
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$(GHDL) -a $(GHDLFLAGS) --workdir=$(shell dirname $@) $<
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common.o: decode_types.o
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control.o: gpr_hazard.o cr_hazard.o common.o
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sim_jtag.o: sim_jtag_socket.o
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core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
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core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o loadstore1.o dcache.o writeback.o core_debug.o
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core_debug.o: common.o
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countzero.o:
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countzero_tb.o: common.o glibc_random.o countzero.o
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cr_file.o: common.o
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crhelpers.o: common.o
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decode1.o: common.o decode_types.o
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decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
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decode_types.o:
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execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o multiply.o divider.o
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fetch1.o: common.o
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fetch2.o: common.o wishbone_types.o
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glibc_random_helpers.o:
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glibc_random.o: glibc_random_helpers.o
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helpers.o:
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cache_ram.o:
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plru.o:
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plru_tb.o: plru.o
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utils.o:
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sim_bram.o: sim_bram_helpers.o utils.o
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wishbone_bram_wrapper.o: wishbone_types.o sim_bram.o utils.o
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wishbone_bram_tb.o: wishbone_bram_wrapper.o
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icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
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icache_tb.o: common.o wishbone_types.o icache.o wishbone_bram_wrapper.o
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dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
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dcache_tb.o: common.o wishbone_types.o dcache.o wishbone_bram_wrapper.o
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insn_helpers.o:
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loadstore1.o: common.o helpers.o decode_types.o
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logical.o: decode_types.o
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multiply_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o multiply.o
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multiply.o: common.o decode_types.o
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divider_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o divider.o
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divider.o: common.o decode_types.o
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ppc_fx_insns.o: helpers.o
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register_file.o: common.o
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rotator.o: common.o
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rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
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sim_console.o:
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sim_uart.o: wishbone_types.o sim_console.o
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soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o
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wishbone_arbiter.o: wishbone_types.o
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wishbone_types.o:
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writeback.o: common.o crhelpers.o
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dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
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dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
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wishbone_debug_master.o: wishbone_types.o
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UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
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sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
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$(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
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fpga/soc_reset_tb.o: fpga/soc_reset.o
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soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
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$(GHDL) -e $(GHDLFLAGS) --workdir=fpga soc_reset_tb
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core_tb: core_tb.o sim_vhpi_c.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
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fetch_tb: fetch_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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icache_tb: icache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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dcache_tb: dcache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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plru_tb: plru_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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loadstore_tb: loadstore_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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multiply_tb: multiply_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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divider_tb: divider_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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rotator_tb: rotator_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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countzero_tb: countzero_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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simple_ram_tb: simple_ram_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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wishbone_bram_tb: sim_vhpi_c.o sim_bram_helpers_c.o wishbone_bram_tb.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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dmi_dtm_tb: dmi_dtm_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
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$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
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tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
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tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
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check: $(tests) $(test_console) test_micropython test_micropython_long
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check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long $(tests_console)
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$(tests): core_tb
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@./scripts/run_test.sh $@
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$(tests_console): core_tb
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@./scripts/run_test_console.sh $@
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test_micropython: core_tb
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@./scripts/test_micropython.py
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test_micropython_long: core_tb
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@./scripts/test_micropython_long.py
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TAGS:
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find . -name '*.vhdl' | xargs ./scripts/vhdltags
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.PHONY: TAGS
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clean:
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rm -f *.o work-*cf unisim-*cf $(all)
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rm -f fpga/*.o fpga/work-*cf
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rm -f sim-unisim/*.o sim-unisim/unisim-*cf
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rm -f TAGS
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distclean: clean
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rm -f *~ fpga/~
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