mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-01-11 23:43:15 +00:00
554b753172
This adds a local socket that can be used to communicate with the debug tool (which will be committed separately) and generates the JTAG signals. We generate the low level JTAG signals, thus directly driving the simulated BSCANE2, and the Xilinx DTM Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
25 lines
1019 B
VHDL
25 lines
1019 B
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
package sim_jtag_socket is
|
|
procedure sim_jtag_read_msg(out_msg : out std_ulogic_vector(247 downto 0);
|
|
out_size : out std_ulogic_vector(7 downto 0));
|
|
attribute foreign of sim_jtag_read_msg : procedure is "VHPIDIRECT sim_jtag_read_msg";
|
|
procedure sim_jtag_write_msg(in_msg : in std_ulogic_vector(247 downto 0);
|
|
in_size : in std_ulogic_vector(7 downto 0));
|
|
attribute foreign of sim_jtag_write_msg : procedure is "VHPIDIRECT sim_jtag_write_msg";
|
|
end sim_jtag_socket;
|
|
|
|
package body sim_jtag_socket is
|
|
procedure sim_jtag_read_msg(out_msg : out std_ulogic_vector(247 downto 0);
|
|
out_size : out std_ulogic_vector(7 downto 0)) is
|
|
begin
|
|
assert false report "VHPI" severity failure;
|
|
end sim_jtag_read_msg;
|
|
procedure sim_jtag_write_msg(in_msg : in std_ulogic_vector(247 downto 0);
|
|
in_size : in std_ulogic_vector(7 downto 0)) is
|
|
begin
|
|
assert false report "VHPI" severity failure;
|
|
end sim_jtag_write_msg;
|
|
end sim_jtag_socket;
|