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310a56c0766a778ea1e5397ea015fa71d767c221
antonblanchard.microwatt/fpga
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Benjamin Herrenschmidt 310a56c076 Re-indent and reformat soc.vhdl 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-10 16:50:49 +01:00
..
arty_a7-35.xdc
Merge pull request #20 from antonblanchard/reset-rework2
2019-09-08 16:34:10 +10:00
clk_gen_bypass.vhd
Rework SOC reset
2019-09-08 07:40:19 +10:00
clk_gen_mcmm.vhd
Cmod A7-35 support
2019-09-08 16:36:50 +10:00
clk_gen_plle2.vhd
Rework SOC reset
2019-09-08 07:40:19 +10:00
cmod_a7-35.xdc
Cmod A7-35 support
2019-09-08 16:36:50 +10:00
firmware.hex
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
hello_world.hex
Rebuild hello world assuming a 50MHz clock
2019-08-26 22:09:28 +10:00
LICENSE
Initial import of microwatt
2019-08-22 16:46:13 +10:00
nexys_a7.xdc
Merge pull request #20 from antonblanchard/reset-rework2
2019-09-08 16:34:10 +10:00
nexys-video.xdc
Rename a few reset signals
2019-09-07 21:33:50 +10:00
nodivide.patch
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
pp_fifo.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
pp_soc_memory.vhd
Fix ghdl build error with pp_soc_memory
2019-08-27 22:12:33 +10:00
pp_soc_uart.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
pp_utilities.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
soc_reset_tb.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc_reset.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc.vhdl
Re-indent and reformat soc.vhdl
2019-09-10 16:50:49 +01:00
toplevel.vhdl
Split FPGA toplevel from soc
2019-09-10 16:50:49 +01:00