mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-02-13 19:34:22 +00:00
a69a93b466
This will be useful when we start needing different toplevels for different boards. We keep the reset and clock generators in the toplevel as they will eventually be taken over by litedram when we integrate it, and they are more likely to change on different system types. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
118 lines
2.7 KiB
Core
118 lines
2.7 KiB
Core
CAPI=2:
|
|
|
|
name : ::microwatt:0
|
|
|
|
filesets:
|
|
core:
|
|
files:
|
|
- decode_types.vhdl
|
|
- wishbone_types.vhdl
|
|
- common.vhdl
|
|
- fetch1.vhdl
|
|
- fetch2.vhdl
|
|
- decode1.vhdl
|
|
- helpers.vhdl
|
|
- decode2.vhdl
|
|
- register_file.vhdl
|
|
- cr_file.vhdl
|
|
- crhelpers.vhdl
|
|
- ppc_fx_insns.vhdl
|
|
- sim_console.vhdl
|
|
- execute1.vhdl
|
|
- execute2.vhdl
|
|
- loadstore1.vhdl
|
|
- loadstore2.vhdl
|
|
- multiply.vhdl
|
|
- writeback.vhdl
|
|
- wishbone_arbiter.vhdl
|
|
- insn_helpers.vhdl
|
|
- core.vhdl
|
|
file_type : vhdlSource-2008
|
|
|
|
soc:
|
|
files:
|
|
- fpga/pp_fifo.vhd
|
|
- fpga/pp_soc_memory.vhd
|
|
- fpga/soc_reset.vhdl
|
|
- fpga/pp_soc_uart.vhd
|
|
- fpga/pp_utilities.vhd
|
|
- fpga/soc.vhdl
|
|
- fpga/toplevel.vhdl
|
|
- fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
|
|
file_type : vhdlSource-2008
|
|
|
|
nexys_a7:
|
|
files:
|
|
- fpga/nexys_a7.xdc : {file_type : xdc}
|
|
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
|
|
|
|
nexys_video:
|
|
files:
|
|
- fpga/nexys-video.xdc : {file_type : xdc}
|
|
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
|
|
|
|
arty_a7-35:
|
|
files:
|
|
- fpga/arty_a7-35.xdc : {file_type : xdc}
|
|
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
|
|
|
|
cmod_a7-35:
|
|
files:
|
|
- fpga/cmod_a7-35.xdc : {file_type : xdc}
|
|
- fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
|
|
|
|
targets:
|
|
nexys_a7:
|
|
default_tool: vivado
|
|
filesets: [core, nexys_a7, soc]
|
|
parameters : [memory_size, ram_init_file]
|
|
tools:
|
|
vivado: {part : xc7a100tcsg324-1}
|
|
toplevel : toplevel
|
|
|
|
nexys_video:
|
|
default_tool: vivado
|
|
filesets: [core, nexys_video, soc]
|
|
parameters : [memory_size, ram_init_file]
|
|
tools:
|
|
vivado: {part : xc7a200tsbg484-1}
|
|
toplevel : toplevel
|
|
|
|
arty_a7-35:
|
|
default_tool: vivado
|
|
filesets: [core, arty_a7-35, soc]
|
|
parameters : [memory_size, ram_init_file]
|
|
tools:
|
|
vivado: {part : xc7a35ticsg324-1L}
|
|
toplevel : toplevel
|
|
|
|
cmod_a7-35:
|
|
default_tool: vivado
|
|
filesets: [core, cmod_a7-35, soc]
|
|
parameters : [memory_size, ram_init_file, reset_low=false]
|
|
tools:
|
|
vivado: {part : xc7a35tcpg236-1}
|
|
toplevel : toplevel
|
|
|
|
synth:
|
|
filesets: [core]
|
|
tools:
|
|
vivado: {pnr : none}
|
|
toplevel: core
|
|
|
|
parameters:
|
|
memory_size:
|
|
datatype : int
|
|
description : On-chip memory size (bytes)
|
|
paramtype : generic
|
|
|
|
ram_init_file:
|
|
datatype : file
|
|
description : Initial on-chip RAM contents
|
|
paramtype : generic
|
|
|
|
reset_low:
|
|
datatype : bool
|
|
description : External reset button polarity
|
|
paramtype : generic
|