Benjamin Herrenschmidt 48e6e719d3 Multiply needs to be 16 stages to fix all timing issues ...

This seems dependent on the FPGA type/size, so we should probably
make it a toplevel generic, but for now this helps on the
Arty A7-35

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2019-09-30 13:54:32 +10:00

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