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antonblanchard.microwatt/wishbone_debug_master.vhdl
Benjamin Herrenschmidt b46f81fae4 Wishbone debug module 
This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-20 15:07:49 +10:00

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