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antonblanchard.microwatt/fpga
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Anton Blanchard 6cbf456388 SOC memory wishbone should clear ACK regardless of STB 
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2019-09-12 15:57:00 +10:00
..
arty_a7-35.xdc
Merge pull request #20 from antonblanchard/reset-rework2
2019-09-08 16:34:10 +10:00
clk_gen_bypass.vhd
Fix clk_gen_bypass
2019-09-12 12:25:18 +10:00
clk_gen_mcmm.vhd
Remove names from end record statements
2019-09-12 09:04:02 +10:00
clk_gen_plle2.vhd
Remove names from end record statements
2019-09-12 09:04:02 +10:00
cmod_a7-35.xdc
Cmod A7-35 support
2019-09-08 16:36:50 +10:00
firmware.hex
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
hello_world.hex
Rebuild hello world assuming a 50MHz clock
2019-08-26 22:09:28 +10:00
LICENSE
Initial import of microwatt
2019-08-22 16:46:13 +10:00
mw_soc_memory.vhdl
SOC memory wishbone should clear ACK regardless of STB
2019-09-12 15:57:00 +10:00
nexys_a7.xdc
Merge pull request #20 from antonblanchard/reset-rework2
2019-09-08 16:34:10 +10:00
nexys-video.xdc
Rename a few reset signals
2019-09-07 21:33:50 +10:00
nodivide.patch
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
pp_fifo.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
pp_soc_uart.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
pp_utilities.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
soc_reset_tb.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc_reset.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
toplevel.vhdl
Share soc.vhdl between FPGA and sim
2019-09-10 16:57:47 +01:00