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741b2e42ac02f70388ee513ede2ce8a880ee88c3
antonblanchard.microwatt/fpga
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Boris Shingarov 679c547e5f fpga: Add support for Genesys2 
Signed-off-by: Boris Shingarov <shingarov@labware.com>
2020-08-07 15:42:28 +10:00
..
acorn-cle-215.xdc
acorn: Add support for the Acorn CLE 215+
2020-08-07 15:42:07 +10:00
arty_a7.xdc
uart: Import and hook up opencore 16550 compatible UART
2020-06-24 09:53:46 +10:00
clk_gen_bypass.vhd
Fix clk_gen_bypass
2019-10-13 14:41:53 +11:00
clk_gen_ecp5.vhd
Add PLL for ECP5 device
2020-07-07 22:28:58 +10:00
clk_gen_mcmm.vhd
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00
clk_gen_plle2.vhd
acorn: Add support for the Acorn CLE 215+
2020-08-07 15:42:07 +10:00
cmod_a7-35.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
firmware.hex
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
genesys2.xdc
fpga: Add support for Genesys2
2020-08-07 15:42:28 +10:00
hello_world.hex
hello_world: Use new headers and frequency from syscon
2020-05-08 21:06:16 +10:00
LICENSE
Initial import of microwatt
2019-08-22 16:46:13 +10:00
main_bram.vhdl
Fix some ghdlsynth issues with fpga_bram
2020-01-11 14:34:25 +11:00
nexys_a7.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
nexys-video.xdc
spi: Add SPI Flash controller
2020-06-13 00:01:48 +10:00
pp_fifo.vhd
pp_fifo: Fix full fifo losing all data on simultaneous push & pop
2020-05-15 20:49:09 +10:00
pp_soc_uart.vhd
uart: Remove combinational loops on ack and stall signal
2020-06-13 11:38:34 +10:00
pp_utilities.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
soc_reset_tb.vhdl
Exit cleanly from testbench on success
2020-05-20 16:07:13 +10:00
soc_reset.vhdl
soc_reset: Use counters, add synchronizers
2020-05-16 12:42:58 +10:00
top-acorn-cle-215.vhdl
acorn: Add support for the Acorn CLE 215+
2020-08-07 15:42:07 +10:00
top-arty.vhdl
litedram: l2: Add support for more geometries
2020-07-08 16:47:30 +10:00
top-generic.vhdl
uart: Make 16550 the default
2020-06-26 08:17:18 +10:00
top-genesys2.vhdl
fpga: Add support for Genesys2
2020-08-07 15:42:28 +10:00
top-nexys-video.vhdl
litedram: l2: Add support for more geometries
2020-07-08 16:47:30 +10:00