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antonblanchard.microwatt/fpga
Benjamin Herrenschmidt 7560e8f2ff arty/nexys: Rework reset with litedram
When using litedram, request a much longer PLL reset. This seems to
help get rid of all the grabled output after config.

Also use the clean system_rst out of litedram as our source of reset
for the rest of the SoC (it is synchronized with system_clk and takes
pll_locked into account already)
2020-05-16 12:42:58 +10:00
..
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