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https://github.com/antonblanchard/microwatt.git
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d4f51e08c8
This adds logic to detect the cases where the quotient of the division overflows the range of the output representation, and return all zeroes in those cases, which is what POWER9 does. To do this, we extend the dividend register by 1 bit and we do an extra step in the division process to get a 2^64 bit of the quotient, which ends up in the 'overflow' signal. This catches all the cases where dividend >= 2^64 * divisor, including the case where divisor = 0, and the divde/divdeu cases where |RA| >= |RB|. Then, in the output stage, we also check that the result fits in the representable range, which depends on whether the division is a signed division or not, and whether it is a 32-bit or 64-bit division. If dividend >= 2^64 or the result doesn't fit in the representable range, write_data is set to 0 and write_cr_data to 0x20000000 (i.e. cr0.eq = 1). POWER9 sets the top 32 bits of the result to zero for 32-bit signed divisions, and sets CR0 when RC=1 according to the 64-bit value (i.e. CR0.LT is always 0 for 32-bit signed divisions, even if the 32-bit result is negative). However, modsw with a negative result sets the top 32 bits to all 1s. We follow suit. This updates divider_tb to check the invalid cases as well as the valid case. This also fixes a small bug where the reset signal for the divider was driven from rst when it should have been driven from core_rst. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
576 lines
23 KiB
VHDL
576 lines
23 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.glibc_random.all;
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use work.ppc_fx_insns.all;
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entity divider_tb is
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end divider_tb;
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architecture behave of divider_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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constant clk_period : time := 10 ns;
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signal d1 : Decode2ToDividerType;
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signal d2 : DividerToWritebackType;
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begin
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divider_0: entity work.divider
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port map (clk => clk, rst => rst, d_in => d1, d_out => d2);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
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variable si: std_ulogic_vector(15 downto 0);
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variable d128: std_ulogic_vector(127 downto 0);
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variable q128: std_ulogic_vector(127 downto 0);
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variable q64: std_ulogic_vector(63 downto 0);
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variable rem32: std_ulogic_vector(31 downto 0);
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begin
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rst <= '1';
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wait for clk_period;
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rst <= '0';
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d1.valid <= '1';
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d1.write_reg <= "10001";
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d1.dividend <= x"0000000010001000";
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d1.divisor <= x"0000000000001111";
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d1.is_signed <= '0';
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d1.is_32bit <= '0';
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d1.is_extended <= '0';
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d1.is_modulus <= '0';
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d1.rc <= '0';
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wait for clk_period;
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assert d2.valid = '0';
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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assert d2.write_reg_enable = '1';
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assert d2.write_reg_nr = "10001";
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assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data);
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assert d2.write_cr_enable = '0';
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wait for clk_period;
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assert d2.valid = '0' report "valid";
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d1.valid <= '1';
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d1.rc <= '1';
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wait for clk_period;
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assert d2.valid = '0' report "valid";
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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assert d2.write_reg_enable = '1';
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assert d2.write_reg_nr = "10001";
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assert d2.write_reg_data = x"000000000000f001" report "result " & to_hstring(d2.write_reg_data);
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assert d2.write_cr_enable = '1';
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assert d2.write_cr_mask = "10000000";
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assert d2.write_cr_data = x"40000000" report "cr data is " & to_hstring(d2.write_cr_data);
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wait for clk_period;
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assert d2.valid = '0';
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-- test divd
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report "test divd";
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divd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"8000000000000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divd(ra, rb);
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divd";
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end loop;
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end loop;
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end loop;
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-- test divdu
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report "test divdu";
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divdu_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divdu(ra, rb);
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divdu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divdu";
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end loop;
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end loop;
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end loop;
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-- test divde
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report "test divde";
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divde_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(signed(d128) / signed(rb));
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if q128(127 downto 63) = x"0000000000000000" & '0' or
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q128(127 downto 63) = x"ffffffffffffffff" & '1' then
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behave_rt := q128(63 downto 0);
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end if;
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divde expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divde";
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end loop;
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end loop;
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end loop;
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-- test divdeu
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report "test divdeu";
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divdeu_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if unsigned(rb) > unsigned(ra) then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb));
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behave_rt := q128(63 downto 0);
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end if;
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assert to_hstring(behave_rt) = to_hstring(d2.write_reg_data)
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report "bad divdeu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divdeu";
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end loop;
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end loop;
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end loop;
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-- test divw
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report "test divw";
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divw_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"ffffffff80000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divw(ra, rb);
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divw";
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end loop;
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end loop;
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end loop;
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-- test divwu
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report "test divwu";
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divwu_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divwu(ra, rb);
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divwu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divwu";
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end loop;
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end loop;
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end loop;
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-- test divwe
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report "test divwe";
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divwe_loop : for vlength in 1 to 4 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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q64 := std_ulogic_vector(signed(ra) / signed(rb));
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if q64(63 downto 31) = x"00000000" & '0' or
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q64(63 downto 31) = x"ffffffff" & '1' then
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behave_rt := x"00000000" & q64(31 downto 0);
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divwe expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divwe";
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end if;
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end loop;
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end loop;
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end loop;
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-- test divweu
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report "test divweu";
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divweu_loop : for vlength in 1 to 4 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then
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behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb));
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad divweu expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data) & " for ra = " & to_hstring(ra) & " rb = " & to_hstring(rb);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for divweu";
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end loop;
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end loop;
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end loop;
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-- test modsd
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report "test modsd";
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modsd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_signed <= '1';
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d1.is_extended <= '0';
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d1.is_32bit <= '0';
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d1.is_modulus <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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assert d2.valid = '1';
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := std_ulogic_vector(signed(ra) rem signed(rb));
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end if;
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assert behave_rt = d2.write_reg_data
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report "bad modsd expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
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assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
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report "bad CR setting for modsd";
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end loop;
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end loop;
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end loop;
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-- test modud
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report "test modud";
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modud_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
|
|
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
|
|
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
|
|
|
|
d1.dividend <= ra;
|
|
d1.divisor <= rb;
|
|
d1.is_signed <= '0';
|
|
d1.is_extended <= '0';
|
|
d1.is_32bit <= '0';
|
|
d1.is_modulus <= '1';
|
|
d1.valid <= '1';
|
|
|
|
wait for clk_period;
|
|
|
|
d1.valid <= '0';
|
|
for j in 0 to 66 loop
|
|
wait for clk_period;
|
|
if d2.valid = '1' then
|
|
exit;
|
|
end if;
|
|
end loop;
|
|
assert d2.valid = '1';
|
|
|
|
behave_rt := (others => '0');
|
|
if rb /= x"0000000000000000" then
|
|
behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb));
|
|
end if;
|
|
assert behave_rt = d2.write_reg_data
|
|
report "bad modud expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
|
assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
|
report "bad CR setting for modud";
|
|
end loop;
|
|
end loop;
|
|
end loop;
|
|
|
|
-- test modsw
|
|
report "test modsw";
|
|
modsw_loop : for dlength in 1 to 4 loop
|
|
for vlength in 1 to dlength loop
|
|
for i in 0 to 100 loop
|
|
ra := std_ulogic_vector(resize(signed(pseudorand(dlength * 8)), 64));
|
|
rb := std_ulogic_vector(resize(signed(pseudorand(vlength * 8)), 64));
|
|
|
|
d1.dividend <= ra;
|
|
d1.divisor <= rb;
|
|
d1.is_signed <= '1';
|
|
d1.is_extended <= '0';
|
|
d1.is_32bit <= '1';
|
|
d1.is_modulus <= '1';
|
|
d1.valid <= '1';
|
|
|
|
wait for clk_period;
|
|
|
|
d1.valid <= '0';
|
|
for j in 0 to 66 loop
|
|
wait for clk_period;
|
|
if d2.valid = '1' then
|
|
exit;
|
|
end if;
|
|
end loop;
|
|
assert d2.valid = '1';
|
|
|
|
behave_rt := (others => '0');
|
|
if rb /= x"0000000000000000" then
|
|
rem32 := std_ulogic_vector(signed(ra(31 downto 0)) rem signed(rb(31 downto 0)));
|
|
if rem32(31) = '0' then
|
|
behave_rt := x"00000000" & rem32;
|
|
else
|
|
behave_rt := x"ffffffff" & rem32;
|
|
end if;
|
|
end if;
|
|
assert behave_rt = d2.write_reg_data
|
|
report "bad modsw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
|
assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
|
report "bad CR setting for modsw";
|
|
end loop;
|
|
end loop;
|
|
end loop;
|
|
|
|
-- test moduw
|
|
report "test moduw";
|
|
moduw_loop : for dlength in 1 to 4 loop
|
|
for vlength in 1 to dlength loop
|
|
for i in 0 to 100 loop
|
|
ra := std_ulogic_vector(resize(unsigned(pseudorand(dlength * 8)), 64));
|
|
rb := std_ulogic_vector(resize(unsigned(pseudorand(vlength * 8)), 64));
|
|
|
|
d1.dividend <= ra;
|
|
d1.divisor <= rb;
|
|
d1.is_signed <= '0';
|
|
d1.is_extended <= '0';
|
|
d1.is_32bit <= '1';
|
|
d1.is_modulus <= '1';
|
|
d1.valid <= '1';
|
|
|
|
wait for clk_period;
|
|
|
|
d1.valid <= '0';
|
|
for j in 0 to 66 loop
|
|
wait for clk_period;
|
|
if d2.valid = '1' then
|
|
exit;
|
|
end if;
|
|
end loop;
|
|
assert d2.valid = '1';
|
|
|
|
behave_rt := (others => '0');
|
|
if rb /= x"0000000000000000" then
|
|
behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0)));
|
|
end if;
|
|
assert behave_rt(31 downto 0) = d2.write_reg_data(31 downto 0)
|
|
report "bad moduw expected " & to_hstring(behave_rt) & " got " & to_hstring(d2.write_reg_data);
|
|
assert ppc_cmpi('1', behave_rt, x"0000") & x"0000000" = d2.write_cr_data
|
|
report "bad CR setting for moduw";
|
|
end loop;
|
|
end loop;
|
|
end loop;
|
|
|
|
assert false report "end of test" severity failure;
|
|
wait;
|
|
end process;
|
|
end behave;
|