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antonblanchard.microwatt/asic
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Anton Blanchard 795d57249f ASIC: Reduce multiplier from 4 to 2 cycles 
Our sky130 gate level multiply/adder now makes timing with a single
register stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2022-08-22 14:43:21 +10:00
..
behavioural
ASIC: Reduce multiplier from 4 to 2 cycles
2022-08-22 14:43:21 +10:00
cache_ram.vhdl
Add arrays for ASIC flow
2022-08-22 14:43:21 +10:00
main_bram.vhdl
Move register stage back after the RAM
2022-08-22 14:43:21 +10:00
microwatt_asic-verilator.cpp
Add ASIC target
2022-08-22 14:43:21 +10:00
multiply.vhdl
ASIC: Reduce multiplier from 4 to 2 cycles
2022-08-22 14:43:21 +10:00
register_file.vhdl
Add arrays for ASIC flow
2022-08-22 14:43:21 +10:00
top-asic.vhdl
Add simplebus
2022-08-22 14:43:21 +10:00