Anton Blanchard
795d57249f
ASIC: Reduce multiplier from 4 to 2 cycles
...
Our sky130 gate level multiply/adder now makes timing with a single
register stage.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com >
2022-08-22 14:43:21 +10:00
Anton Blanchard
4fc321cd41
Move register stage back after the RAM
...
The 512x64 DFFRAM has quite big hold violations that we can hopefully
work around by removing the register stage before the RAM.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com >
2022-08-22 14:43:21 +10:00
Anton Blanchard
d2cc31cde4
Add simplebus
...
Signed-off-by: Anton Blanchard <anton@linux.ibm.com >
2022-08-22 14:43:21 +10:00
Anton Blanchard
6745d9dd5f
Hook up JTAG to ASIC top level
...
Signed-off-by: Anton Blanchard <anton@linux.ibm.com >
2022-08-22 14:43:21 +10:00
Anton Blanchard
28debecf1a
Add ASIC target
...
Signed-off-by: Anton Blanchard <anton@linux.ibm.com >
2022-08-22 14:43:21 +10:00
Anton Blanchard
01f8ad55ef
Move register stage from after RAM to before RAM
...
Signed-off-by: Anton Blanchard <anton@linux.ibm.com >
2022-08-22 14:43:21 +10:00
Anton Blanchard
52f2462232
Add arrays for ASIC flow
...
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com >
2022-08-22 14:43:21 +10:00
