github.com/antonblanchard.microwatt
1
0
Fork 0
mirror of https://github.com/antonblanchard/microwatt.git synced 2026-03-08 03:29:30 +00:00
Code Releases Activity
Files
cc532dd06508e40fb3575cd33b5d0e1b16cd929b
antonblanchard.microwatt/fpga
History
Anton Blanchard f96d179f66 Some yosys fixes 
This gets the yosys build further along, but I'm now chasing what looks
like a yosys bug.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-05-19 10:23:58 +10:00
..
arty_a7.xdc
fpga: Hookup Arty to litedram
2020-05-08 21:06:16 +10:00
clk_gen_bypass.vhd
Fix clk_gen_bypass
2019-10-13 14:41:53 +11:00
clk_gen_mcmm.vhd
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00
clk_gen_plle2.vhd
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00
cmod_a7-35.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
firmware.hex
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
hello_world.hex
hello_world: Use new headers and frequency from syscon
2020-05-08 21:06:16 +10:00
LICENSE
Initial import of microwatt
2019-08-22 16:46:13 +10:00
main_bram.vhdl
Fix some ghdlsynth issues with fpga_bram
2020-01-11 14:34:25 +11:00
nexys_a7.xdc
Add SPI configuration to Xilinx constraint files
2019-12-09 16:12:37 +11:00
nexys-video.xdc
fpga: Hookup nexys-video to litedram
2020-05-08 21:06:16 +10:00
pp_fifo.vhd
fifo: Reformat
2019-10-13 12:57:23 +11:00
pp_soc_uart.vhd
Add a few FFs on the RX input to avoid metastability issues
2020-01-19 22:34:24 +11:00
pp_utilities.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
soc_reset_tb.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc_reset.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
top-arty.vhdl
syscon: Add syscon registers
2020-05-08 21:06:16 +10:00
top-generic.vhdl
Some yosys fixes
2020-05-19 10:23:58 +10:00
top-nexys-video.vhdl
syscon: Add syscon registers
2020-05-08 21:06:16 +10:00