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9d285a265c
This adds code to loadstore1 to convert between single-precision and double-precision formats, and implements the lfs* and stfs* instructions. The conversion processes are described in Power ISA v3.1 Book 1 sections 4.6.2 and 4.6.3. These conversions take one cycle, so lfs* and stfs* are one cycle slower than lfd* and stfd*. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
61 lines
1.6 KiB
VHDL
61 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.helpers.all;
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entity zero_counter is
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port (
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clk : in std_logic;
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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is_32bit : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity zero_counter;
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architecture behaviour of zero_counter is
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signal inp : std_ulogic_vector(63 downto 0);
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signal sum : std_ulogic_vector(64 downto 0);
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signal msb_r : std_ulogic;
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signal onehot : std_ulogic_vector(63 downto 0);
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signal onehot_r : std_ulogic_vector(63 downto 0);
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signal bitnum : std_ulogic_vector(5 downto 0);
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begin
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countzero_r: process(clk)
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begin
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if rising_edge(clk) then
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msb_r <= sum(64);
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onehot_r <= onehot;
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end if;
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end process;
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countzero: process(all)
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begin
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if is_32bit = '0' then
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if count_right = '0' then
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inp <= bit_reverse(rs);
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else
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inp <= rs;
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end if;
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else
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inp(63 downto 32) <= x"FFFFFFFF";
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if count_right = '0' then
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inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
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else
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inp(31 downto 0) <= rs(31 downto 0);
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end if;
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end if;
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sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
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onehot <= sum(63 downto 0) and inp;
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-- The following occurs after a clock edge
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bitnum <= bit_number(onehot_r);
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result <= x"00000000000000" & "0" & msb_r & bitnum;
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end process;
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end behaviour;
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