Paul Mackerras 0ceace927c Xilinx FPGAs: Eliminate Vivado critical warnings ...

This resolves various warnings and critical warnings from Vivado.

In particular, the asynchronous loops in the xilinx hardware RNG were
giving a lot of critical warnings, which proved to be difficult to
suppress, so this instead makes all the xilinx platforms use the
'nonrandom.vhdl' implementation, which always returns an error.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

2024-04-05 17:20:43 +11:00

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