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removed most traces of direct access to the m68ki_cpu global variable

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This commit is contained in:
Rune Holm
2021-06-20 21:34:59 +02:00
parent 0c763fca70
commit 747b19f7c8
4 changed files with 238 additions and 238 deletions
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38
m68k_in.c
View File

@@ -6931,7 +6931,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x003: /* TC */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_tc;
REG_DA[(word2 >> 12) & 15] = state->mmu_tc;
return;
}
m68ki_exception_illegal(state);
@@ -6939,7 +6939,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x004: /* ITT0 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt0;
REG_DA[(word2 >> 12) & 15] = state->mmu_itt0;
return;
}
m68ki_exception_illegal(state);
@@ -6947,7 +6947,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x005: /* ITT1 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_itt1;
REG_DA[(word2 >> 12) & 15] = state->mmu_itt1;
return;
}
m68ki_exception_illegal(state);
@@ -6955,7 +6955,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x006: /* DTT0 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt0;
REG_DA[(word2 >> 12) & 15] = state->mmu_dtt0;
return;
}
m68ki_exception_illegal(state);
@@ -6963,7 +6963,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x007: /* DTT1 */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_dtt1;
REG_DA[(word2 >> 12) & 15] = state->mmu_dtt1;
return;
}
m68ki_exception_illegal(state);
@@ -6971,7 +6971,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x805: /* MMUSR */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_sr_040;
REG_DA[(word2 >> 12) & 15] = state->mmu_sr_040;
return;
}
m68ki_exception_illegal(state);
@@ -6979,7 +6979,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x806: /* URP */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_urp_aptr;
REG_DA[(word2 >> 12) & 15] = state->mmu_urp_aptr;
return;
}
m68ki_exception_illegal(state);
@@ -6987,7 +6987,7 @@ M68KMAKE_OP(movec, 32, cr, .)
case 0x807: /* SRP */
if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
REG_DA[(word2 >> 12) & 15] = m68ki_cpu.mmu_srp_aptr;
REG_DA[(word2 >> 12) & 15] = state->mmu_srp_aptr;
return;
}
m68ki_exception_illegal(state);
@@ -7090,15 +7090,15 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x003: /* TC */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_tc = REG_DA[(word2 >> 12) & 15];
state->mmu_tc = REG_DA[(word2 >> 12) & 15];
if (m68ki_cpu.mmu_tc & 0x8000)
if (state->mmu_tc & 0x8000)
{
m68ki_cpu.pmmu_enabled = 1;
state->pmmu_enabled = 1;
}
else
{
m68ki_cpu.pmmu_enabled = 0;
state->pmmu_enabled = 0;
}
return;
}
@@ -7107,7 +7107,7 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x004: /* ITT0 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_itt0 = REG_DA[(word2 >> 12) & 15];
state->mmu_itt0 = REG_DA[(word2 >> 12) & 15];
return;
}
m68ki_exception_illegal(state);
@@ -7115,7 +7115,7 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x005: /* ITT1 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_itt1 = REG_DA[(word2 >> 12) & 15];
state->mmu_itt1 = REG_DA[(word2 >> 12) & 15];
return;
}
m68ki_exception_illegal(state);
@@ -7123,7 +7123,7 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x006: /* DTT0 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_dtt0 = REG_DA[(word2 >> 12) & 15];
state->mmu_dtt0 = REG_DA[(word2 >> 12) & 15];
return;
}
m68ki_exception_illegal(state);
@@ -7131,7 +7131,7 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x007: /* DTT1 */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_dtt1 = REG_DA[(word2 >> 12) & 15];
state->mmu_dtt1 = REG_DA[(word2 >> 12) & 15];
return;
}
m68ki_exception_illegal(state);
@@ -7139,7 +7139,7 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x805: /* MMUSR */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_sr_040 = REG_DA[(word2 >> 12) & 15];
state->mmu_sr_040 = REG_DA[(word2 >> 12) & 15];
return;
}
m68ki_exception_illegal(state);
@@ -7147,7 +7147,7 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x806: /* URP */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_urp_aptr = REG_DA[(word2 >> 12) & 15];
state->mmu_urp_aptr = REG_DA[(word2 >> 12) & 15];
return;
}
m68ki_exception_illegal(state);
@@ -7155,7 +7155,7 @@ M68KMAKE_OP(movec, 32, rc, .)
case 0x807: /* SRP */
if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
{
m68ki_cpu.mmu_srp_aptr = REG_DA[(word2 >> 12) & 15];
state->mmu_srp_aptr = REG_DA[(word2 >> 12) & 15];
return;
}
m68ki_exception_illegal(state);

96
m68kcpu.c
View File

@@ -938,26 +938,26 @@ void m68k_set_cpu_type(struct m68ki_cpu_core *state, unsigned int cpu_type)
case M68K_CPU_TYPE_68LC040:
CPU_TYPE = CPU_TYPE_LC040;
CPU_ADDRESS_MASK = 0xffffffff;
m68ki_cpu.sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
m68ki_cpu.cyc_instruction = m68ki_cycles[4];
m68ki_cpu.cyc_exception = m68ki_exception_cycle_table[4];
m68ki_cpu.cyc_bcc_notake_b = -2;
m68ki_cpu.cyc_bcc_notake_w = 0;
m68ki_cpu.cyc_dbcc_f_noexp = 0;
m68ki_cpu.cyc_dbcc_f_exp = 4;
m68ki_cpu.cyc_scc_r_true = 0;
m68ki_cpu.cyc_movem_w = 2;
m68ki_cpu.cyc_movem_l = 2;
m68ki_cpu.cyc_shift = 0;
m68ki_cpu.cyc_reset = 518;
state->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
state->cyc_instruction = m68ki_cycles[4];
state->cyc_exception = m68ki_exception_cycle_table[4];
state->cyc_bcc_notake_b = -2;
state->cyc_bcc_notake_w = 0;
state->cyc_dbcc_f_noexp = 0;
state->cyc_dbcc_f_exp = 4;
state->cyc_scc_r_true = 0;
state->cyc_movem_w = 2;
state->cyc_movem_l = 2;
state->cyc_shift = 0;
state->cyc_reset = 518;
HAS_PMMU = 1;
HAS_FPU = 0;
return;
}
}
uint m68k_get_address_mask() {
return m68ki_cpu.address_mask;
uint m68k_get_address_mask(m68ki_cpu_core *state) {
return state->address_mask;
}
/* Execute some instructions until we use up num_cycles clock cycles */
@@ -1128,12 +1128,12 @@ void m68k_pulse_bus_error(m68ki_cpu_core *state)
void m68k_pulse_reset(m68ki_cpu_core *state)
{
/* Disable the PMMU/HMMU on reset, if any */
m68ki_cpu.pmmu_enabled = 0;
// m68ki_cpu.hmmu_enabled = 0;
state->pmmu_enabled = 0;
// state->hmmu_enabled = 0;
m68ki_cpu.mmu_tc = 0;
m68ki_cpu.mmu_tt0 = 0;
m68ki_cpu.mmu_tt1 = 0;
state->mmu_tc = 0;
state->mmu_tt0 = 0;
state->mmu_tt1 = 0;
/* Clear all stop levels and eat up all remaining cycles */
CPU_STOPPED = 0;
@@ -1148,7 +1148,7 @@ void m68k_pulse_reset(m68ki_cpu_core *state)
/* Interrupt mask to level 7 */
FLAG_INT_MASK = 0x0700;
CPU_INT_LEVEL = 0;
m68ki_cpu.virq_state = 0;
state->virq_state = 0;
/* Reset VBR */
REG_VBR = 0;
/* Go to supervisor mode */
@@ -1208,9 +1208,9 @@ void m68k_set_context(void* src)
/* Read data immediately following the PC */
inline unsigned int m68k_read_immediate_16(m68ki_cpu_core *state, unsigned int address) {
#if M68K_EMULATE_PREFETCH == OPT_ON
for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
return be16toh(((unsigned short *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
for (int i = 0; i < state->read_ranges; i++) {
if(address >= state->read_addr[i] && address < state->read_upper[i]) {
return be16toh(((unsigned short *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
#endif
@@ -1219,9 +1219,9 @@ inline unsigned int m68k_read_immediate_16(m68ki_cpu_core *state, unsigned int a
}
inline unsigned int m68k_read_immediate_32(m68ki_cpu_core *state, unsigned int address) {
#if M68K_EMULATE_PREFETCH == OPT_ON
for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
return be32toh(((unsigned int *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
for (int i = 0; i < state->read_ranges; i++) {
if(address >= state->read_addr[i] && address < state->read_upper[i]) {
return be32toh(((unsigned int *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
#endif
@@ -1231,27 +1231,27 @@ inline unsigned int m68k_read_immediate_32(m68ki_cpu_core *state, unsigned int a
/* Read data relative to the PC */
inline unsigned int m68k_read_pcrelative_8(m68ki_cpu_core *state, unsigned int address) {
for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
return m68ki_cpu.read_data[i][address - m68ki_cpu.read_addr[i]];
for (int i = 0; i < state->read_ranges; i++) {
if(address >= state->read_addr[i] && address < state->read_upper[i]) {
return state->read_data[i][address - state->read_addr[i]];
}
}
return m68k_read_memory_8(address);
}
inline unsigned int m68k_read_pcrelative_16(m68ki_cpu_core *state, unsigned int address) {
for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
return be16toh(((unsigned short *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
for (int i = 0; i < state->read_ranges; i++) {
if(address >= state->read_addr[i] && address < state->read_upper[i]) {
return be16toh(((unsigned short *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
return m68k_read_memory_16(address);
}
inline unsigned int m68k_read_pcrelative_32(m68ki_cpu_core *state, unsigned int address) {
for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
return be32toh(((unsigned int *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
for (int i = 0; i < state->read_ranges; i++) {
if(address >= state->read_addr[i] && address < state->read_upper[i]) {
return be32toh(((unsigned int *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
@@ -1264,20 +1264,20 @@ uint m68ki_read_imm16_addr_slowpath(m68ki_cpu_core *state, uint32_t pc, address_
{
uint32_t address = ADDRESS_68K(pc);
uint32_t pc_address_diff = pc - address;
for (int i = 0; i < m68ki_cpu.read_ranges; i++) {
if(address >= m68ki_cpu.read_addr[i] && address < m68ki_cpu.read_upper[i]) {
cache->lower = m68ki_cpu.read_addr[i] + pc_address_diff;
cache->upper = m68ki_cpu.read_upper[i] + pc_address_diff;
cache->offset = m68ki_cpu.read_data[i] - cache->lower;
for (int i = 0; i < state->read_ranges; i++) {
if(address >= state->read_addr[i] && address < state->read_upper[i]) {
cache->lower = state->read_addr[i] + pc_address_diff;
cache->upper = state->read_upper[i] + pc_address_diff;
cache->offset = state->read_data[i] - cache->lower;
REG_PC += 2;
return be16toh(((unsigned short *)(m68ki_cpu.read_data[i] + (address - m68ki_cpu.read_addr[i])))[0]);
return be16toh(((unsigned short *)(state->read_data[i] + (address - state->read_addr[i])))[0]);
}
}
m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
m68ki_cpu.mmu_tmp_fc = FLAG_S | FUNCTION_CODE_USER_PROGRAM;
m68ki_cpu.mmu_tmp_rw = 1;
m68ki_cpu.mmu_tmp_sz = M68K_SZ_WORD;
state->mmu_tmp_fc = FLAG_S | FUNCTION_CODE_USER_PROGRAM;
state->mmu_tmp_rw = 1;
state->mmu_tmp_sz = M68K_SZ_WORD;
m68ki_check_address_error(state, REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
#if M68K_EMULATE_PREFETCH
@@ -1286,16 +1286,16 @@ uint m68ki_read_imm16_addr_slowpath(m68ki_cpu_core *state, uint32_t pc, address_
if(REG_PC != CPU_PREF_ADDR)
{
CPU_PREF_DATA = m68ki_ic_readimm16(state, REG_PC);
CPU_PREF_ADDR = m68ki_cpu.mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
CPU_PREF_ADDR = state->mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
}
result = MASK_OUT_ABOVE_16(CPU_PREF_DATA);
REG_PC += 2;
if (!m68ki_cpu.mmu_tmp_buserror_occurred) {
if (!state->mmu_tmp_buserror_occurred) {
// prefetch only if no bus error occurred in opcode fetch
CPU_PREF_DATA = m68ki_ic_readimm16(state, REG_PC);
CPU_PREF_ADDR = m68ki_cpu.mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
CPU_PREF_ADDR = state->mmu_tmp_buserror_occurred ? ((uint32)~0) : REG_PC;
// ignore bus error on prefetch
m68ki_cpu.mmu_tmp_buserror_occurred = 0;
state->mmu_tmp_buserror_occurred = 0;
}
return result;
}

14
m68kfpu.c
View File

@@ -251,7 +251,7 @@ static inline void store_pack_float80(m68ki_cpu_core *state, uint32 ea, int k, f
{
dw2 &= pkmask2[17];
dw3 &= pkmask3[17];
// m68ki_cpu.fpcr |= (need to set OPERR bit)
// state->fpcr |= (need to set OPERR bit)
}
}
@@ -2078,7 +2078,7 @@ static void fbcc32(m68ki_cpu_core *state)
void m68040_fpu_op0(m68ki_cpu_core *state)
{
m68ki_cpu.fpu_just_reset = 0;
state->fpu_just_reset = 0;
switch ((REG_IR >> 6) & 0x3)
{
@@ -2150,7 +2150,7 @@ void m68040_fpu_op0(m68ki_cpu_core *state)
static int perform_fsave(m68ki_cpu_core *state, uint32 addr, int inc)
{
if(m68ki_cpu.cpu_type & CPU_TYPE_040)
if(state->cpu_type & CPU_TYPE_040)
{
if(inc)
{
@@ -2205,12 +2205,12 @@ static void do_frestore_null(m68ki_cpu_core *state)
// Mac IIci at 408458e6 wants an FSAVE of a just-restored NULL frame to also be NULL
// The PRM says it's possible to generate a NULL frame, but not how/when/why. (need the 68881/68882 manual!)
m68ki_cpu.fpu_just_reset = 1;
state->fpu_just_reset = 1;
}
void m68040_do_fsave(m68ki_cpu_core *state, uint32 addr, int reg, int inc)
{
if (m68ki_cpu.fpu_just_reset)
if (state->fpu_just_reset)
{
m68ki_write_32(state, addr, 0);
}
@@ -2230,11 +2230,11 @@ void m68040_do_frestore(m68ki_cpu_core *state, uint32 addr, int reg)
if (temp & 0xff000000)
{
// we don't handle non-nullptr frames
m68ki_cpu.fpu_just_reset = 0;
state->fpu_just_reset = 0;
if (reg != -1)
{
uint8 m40 = !!(m68ki_cpu.cpu_type & CPU_TYPE_040);
uint8 m40 = !!(state->cpu_type & CPU_TYPE_040);
// how about an IDLE frame?
if (!m40 && ((temp & 0x00ff0000) == 0x00180000))
{

328
m68kmmu.h
View File

@@ -122,12 +122,12 @@ uint32 DECODE_EA_32(m68ki_cpu_core *state, int ea)
void pmmu_set_buserror(m68ki_cpu_core *state, uint32 addr_in)
{
if (!m_side_effects_disabled && ++m68ki_cpu.mmu_tmp_buserror_occurred == 1)
if (!m_side_effects_disabled && ++state->mmu_tmp_buserror_occurred == 1)
{
m68ki_cpu.mmu_tmp_buserror_address = addr_in;
m68ki_cpu.mmu_tmp_buserror_rw = m68ki_cpu.mmu_tmp_rw;
m68ki_cpu.mmu_tmp_buserror_fc = m68ki_cpu.mmu_tmp_fc;
m68ki_cpu.mmu_tmp_buserror_sz = m68ki_cpu.mmu_tmp_sz;
state->mmu_tmp_buserror_address = addr_in;
state->mmu_tmp_buserror_rw = state->mmu_tmp_rw;
state->mmu_tmp_buserror_fc = state->mmu_tmp_fc;
state->mmu_tmp_buserror_sz = state->mmu_tmp_sz;
}
}
@@ -136,21 +136,21 @@ void pmmu_set_buserror(m68ki_cpu_core *state, uint32 addr_in)
void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc, int rw)
{
// get page size (i.e. # of bits to ignore); is 10 for Apollo
int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
int ps = (state->mmu_tc >> 20) & 0xf;
uint32 atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | ((logical >> ps) << (ps - 8));
uint32 atc_data = (physical >> ps) << (ps - 8);
if (m68ki_cpu.mmu_tmp_sr & (M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY))
if (state->mmu_tmp_sr & (M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY))
{
atc_data |= M68K_MMU_ATC_BUSERROR;
}
if (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
if (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
{
atc_data |= M68K_MMU_ATC_WRITE_PR;
}
if (!rw && !(m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
if (!rw && !(state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
{
atc_data |= M68K_MMU_ATC_MODIFIED;
}
@@ -159,10 +159,10 @@ void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
// if tag bits and function code match, don't add
if (m68ki_cpu.mmu_atc_tag[i] == atc_tag)
if (state->mmu_atc_tag[i] == atc_tag)
{
MMULOG(("%s: hit, old %08x new %08x\n", __func__, m68ki_cpu.mmu_atc_data[i], atc_data));
m68ki_cpu.mmu_atc_data[i] = atc_data;
MMULOG(("%s: hit, old %08x new %08x\n", __func__, state->mmu_atc_data[i], atc_data));
state->mmu_atc_data[i] = atc_data;
return;
}
}
@@ -171,7 +171,7 @@ void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc
int found = -1;
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
if (!(m68ki_cpu.mmu_atc_tag[i] & M68K_MMU_ATC_VALID))
if (!(state->mmu_atc_tag[i] & M68K_MMU_ATC_VALID))
{
found = i;
break;
@@ -181,30 +181,30 @@ void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc
// did we find an entry? steal one by round-robin then
if (found == -1)
{
found = m68ki_cpu.mmu_atc_rr++;
found = state->mmu_atc_rr++;
if (m68ki_cpu.mmu_atc_rr >= MMU_ATC_ENTRIES)
if (state->mmu_atc_rr >= MMU_ATC_ENTRIES)
{
m68ki_cpu.mmu_atc_rr = 0;
state->mmu_atc_rr = 0;
}
}
// add the entry
MMULOG(("ATC[%2d] add: log %08x -> phys %08x (fc=%d) data=%08x\n",
found, (logical >> ps) << ps, (physical >> ps) << ps, fc, atc_data));
m68ki_cpu.mmu_atc_tag[found] = atc_tag;
m68ki_cpu.mmu_atc_data[found] = atc_data;
state->mmu_atc_tag[found] = atc_tag;
state->mmu_atc_data[found] = atc_data;
}
// pmmu_atc_flush: flush entire ATC
// 7fff0003 001ffd10 80f05750 is what should load
void pmmu_atc_flush(m68ki_cpu_core *state)
{
MMULOG(("ATC flush: pc=%08x\n", m68ki_cpu.ppc));
// std::fill(std::begin(m68ki_cpu.mmu_atc_tag), std::end(m68ki_cpu.mmu_atc_tag), 0);
MMULOG(("ATC flush: pc=%08x\n", state->ppc));
// std::fill(std::begin(state->mmu_atc_tag), std::end(state->mmu_atc_tag), 0);
for(int i=0;i<MMU_ATC_ENTRIES;i++)
m68ki_cpu.mmu_atc_tag[i]=0;
m68ki_cpu.mmu_atc_rr = 0;
state->mmu_atc_tag[i]=0;
state->mmu_atc_rr = 0;
}
int fc_from_modes(m68ki_cpu_core *state, uint16 modes);
@@ -213,7 +213,7 @@ void pmmu_atc_flush_fc_ea(m68ki_cpu_core *state, uint16 modes)
{
unsigned int fcmask = (modes >> 5) & 7;
unsigned int fc = fc_from_modes(state, modes) & fcmask;
unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
unsigned int ps = (state->mmu_tc >> 20) & 0xf;
unsigned int mode = (modes >> 10) & 7;
uint32 ea;
@@ -228,29 +228,29 @@ void pmmu_atc_flush_fc_ea(m68ki_cpu_core *state, uint16 modes)
MMULOG(("flush by fc: %d, mask %d\n", fc, fcmask));
for(int i=0,e;i<MMU_ATC_ENTRIES;i++)
{
e=m68ki_cpu.mmu_atc_tag[i];
e=state->mmu_atc_tag[i];
if ((e & M68K_MMU_ATC_VALID) && ((e >> 24) & fcmask) == fc)
{
MMULOG(("flushing entry %08x\n", e));
m68ki_cpu.mmu_atc_tag[i] = 0;
state->mmu_atc_tag[i] = 0;
}
}
break;
case 6: // flush by fc + ea
ea = DECODE_EA_32(state, m68ki_cpu.ir);
ea = DECODE_EA_32(state, state->ir);
MMULOG(("flush by fc/ea: fc %d, mask %d, ea %08x\n", fc, fcmask, ea));
for(unsigned int i=0,e;i<MMU_ATC_ENTRIES;i++)
{
e=m68ki_cpu.mmu_atc_tag[i];
e=state->mmu_atc_tag[i];
if ((e & M68K_MMU_ATC_VALID) &&
(((e >> 24) & fcmask) == fc) &&
// (((e >> ps) << (ps - 8)) == ((ea >> ps) << (ps - 8))))
( (e << ps) == (ea >> 8 << ps) ))
{
MMULOG(("flushing entry %08x\n", e));
m68ki_cpu.mmu_atc_tag[i] = 0;
state->mmu_atc_tag[i] = 0;
}
}
break;
@@ -265,18 +265,18 @@ void pmmu_atc_flush_fc_ea(m68ki_cpu_core *state, uint16 modes)
uint16 pmmu_atc_lookup(m68ki_cpu_core *state, uint32 addr_in, int fc, uint16 rw, uint32 *addr_out, int ptest)
{
MMULOG(("%s: LOOKUP addr_in=%08x, fc=%d, ptest=%d, rw=%d\n", __func__, addr_in, fc, ptest,rw));
unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf;
unsigned int ps = (state->mmu_tc >> 20) & 0xf;
uint32 atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | ((addr_in >> ps) << (ps - 8));
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
if (m68ki_cpu.mmu_atc_tag[i] != atc_tag)
if (state->mmu_atc_tag[i] != atc_tag)
{
continue;
}
uint32 atc_data = m68ki_cpu.mmu_atc_data[i];
uint32 atc_data = state->mmu_atc_data[i];
if (!ptest && !rw)
{
@@ -287,35 +287,35 @@ uint16 pmmu_atc_lookup(m68ki_cpu_core *state, uint32 addr_in, int fc, uint16 rw,
// entry, and creating a new entry with the M bit set.
if (!(atc_data & M68K_MMU_ATC_MODIFIED))
{
m68ki_cpu.mmu_atc_tag[i] = 0;
state->mmu_atc_tag[i] = 0;
continue;
}
}
m68ki_cpu.mmu_tmp_sr = 0;
state->mmu_tmp_sr = 0;
if (atc_data & M68K_MMU_ATC_MODIFIED)
{
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
state->mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
}
if (atc_data & M68K_MMU_ATC_WRITE_PR)
{
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
state->mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
if (atc_data & M68K_MMU_ATC_BUSERROR)
{
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
state->mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
}
*addr_out = (atc_data << 8) | (addr_in & ~(((uint32)~0) << ps));
MMULOG(("%s: addr_in=%08x, addr_out=%08x, MMU SR %04x\n",
__func__, addr_in, *addr_out, m68ki_cpu.mmu_tmp_sr));
__func__, addr_in, *addr_out, state->mmu_tmp_sr));
return 1;
}
MMULOG(("%s: lookup failed\n", __func__));
if (ptest)
{
m68ki_cpu.mmu_tmp_sr = M68K_MMU_SR_INVALID;
state->mmu_tmp_sr = M68K_MMU_SR_INVALID;
}
return 0;
}
@@ -350,7 +350,7 @@ uint16 pmmu_match_tt(m68ki_cpu_core *state, uint32 addr_in, int fc, uint32 tt, u
return 0;
}
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_TRANSPARENT;
state->mmu_tmp_sr |= M68K_MMU_SR_TRANSPARENT;
return 1;
}
@@ -388,7 +388,7 @@ void update_sr(m68ki_cpu_core *state, int type, uint32 tbl_entry, int fc, uint16
case M68K_MMU_DF_DT_PAGE:
if (tbl_entry & M68K_MMU_DF_MODIFIED)
{
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
state->mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
}
/* FALLTHROUGH */
@@ -399,12 +399,12 @@ void update_sr(m68ki_cpu_core *state, int type, uint32 tbl_entry, int fc, uint16
if (tbl_entry & M68K_MMU_DF_WP)
{
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
state->mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
if (_long && !(fc & 4) && (tbl_entry & M68K_MMU_DF_SUPERVISOR))
{
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_SUPERVISOR_ONLY;
state->mmu_tmp_sr |= M68K_MMU_SR_SUPERVISOR_ONLY;
}
break;
default:
@@ -417,18 +417,18 @@ uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32
uint32 *addr_out, int ptest)
{
int level = 0;
uint32 bits = m68ki_cpu.mmu_tc & 0xffff;
int pagesize = (m68ki_cpu.mmu_tc >> 20) & 0xf;
int is = (m68ki_cpu.mmu_tc >> 16) & 0xf;
uint32 bits = state->mmu_tc & 0xffff;
int pagesize = (state->mmu_tc >> 20) & 0xf;
int is = (state->mmu_tc >> 16) & 0xf;
int bitpos = 12;
int resolved = 0;
int pageshift = is;
addr_in <<= is;
m68ki_cpu.mmu_tablewalk = 1;
state->mmu_tablewalk = 1;
if (m68ki_cpu.mmu_tc & M68K_MMU_TC_FCL)
if (state->mmu_tc & M68K_MMU_TC_FCL)
{
bitpos = 16;
}
@@ -447,8 +447,8 @@ uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32
switch(type)
{
case M68K_MMU_DF_DT_INVALID: // invalid, will cause MMU exception
m68ki_cpu.mmu_tmp_sr = M68K_MMU_SR_INVALID;
MMULOG(("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", m68ki_cpu.ppc, addr_in, *addr_out));
state->mmu_tmp_sr = M68K_MMU_SR_INVALID;
MMULOG(("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", state->ppc, addr_in, *addr_out));
resolved = 1;
break;
@@ -518,7 +518,7 @@ uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32
break;
}
if (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR)
if (state->mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR)
{
// Bus error during page table walking is always fatal
resolved = 1;
@@ -527,13 +527,13 @@ uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32
if (!ptest && !m_side_effects_disabled)
{
if (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
if (!rw && (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
{
resolved = 1;
break;
}
if (!(fc & 4) && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY))
if (!(fc & 4) && (state->mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY))
{
resolved = 1;
break;
@@ -545,10 +545,10 @@ uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32
} while(level < limit && !resolved);
m68ki_cpu.mmu_tmp_sr &= 0xfff0;
m68ki_cpu.mmu_tmp_sr |= level;
MMULOG(("MMU SR after walk: %04X\n", m68ki_cpu.mmu_tmp_sr));
m68ki_cpu.mmu_tablewalk = 0;
state->mmu_tmp_sr &= 0xfff0;
state->mmu_tmp_sr |= level;
MMULOG(("MMU SR after walk: %04X\n", state->mmu_tmp_sr));
state->mmu_tablewalk = 0;
return resolved;
}
@@ -562,12 +562,12 @@ uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8
MMULOG(("%s: addr_in=%08x, fc=%d, ptest=%d, rw=%d, limit=%d, pload=%d\n",
__func__, addr_in, fc, ptest, rw, limit, pload));
m68ki_cpu.mmu_tmp_sr = 0;
state->mmu_tmp_sr = 0;
m68ki_cpu.mmu_last_logical_addr = addr_in;
state->mmu_last_logical_addr = addr_in;
if (pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt0, rw) ||
pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt1, rw) ||
if (pmmu_match_tt(state, addr_in, fc, state->mmu_tt0, rw) ||
pmmu_match_tt(state, addr_in, fc, state->mmu_tt1, rw) ||
fc == 7)
{
return addr_in;
@@ -581,10 +581,10 @@ uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8
if (!ptest && !pload && pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 0))
{
if ((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
if ((state->mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
{
MMULOG(("set atc hit buserror: addr_in=%08x, addr_out=%x, rw=%x, fc=%d, sz=%d\n",
addr_in, addr_out, m68ki_cpu.mmu_tmp_rw, m68ki_cpu.mmu_tmp_fc, m68ki_cpu.mmu_tmp_sz));
addr_in, addr_out, state->mmu_tmp_rw, state->mmu_tmp_fc, state->mmu_tmp_sz));
pmmu_set_buserror(state, addr_in);
}
return addr_out;
@@ -593,15 +593,15 @@ uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8
int type;
uint32 tbl_addr;
// if SRP is enabled and we're in supervisor mode, use it
if ((m68ki_cpu.mmu_tc & M68K_MMU_TC_SRE) && (fc & 4))
if ((state->mmu_tc & M68K_MMU_TC_SRE) && (fc & 4))
{
tbl_addr = m68ki_cpu.mmu_srp_aptr & M68K_MMU_DF_ADDR_MASK;
type = m68ki_cpu.mmu_srp_limit & M68K_MMU_DF_DT;
tbl_addr = state->mmu_srp_aptr & M68K_MMU_DF_ADDR_MASK;
type = state->mmu_srp_limit & M68K_MMU_DF_DT;
}
else // else use the CRP
{
tbl_addr = m68ki_cpu.mmu_crp_aptr & M68K_MMU_DF_ADDR_MASK;
type = m68ki_cpu.mmu_crp_limit & M68K_MMU_DF_DT;
tbl_addr = state->mmu_crp_aptr & M68K_MMU_DF_ADDR_MASK;
type = state->mmu_crp_limit & M68K_MMU_DF_DT;
}
if (!pmmu_walk_tables(state, addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest))
@@ -616,13 +616,13 @@ uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8
return addr_out;
}
if ((m68ki_cpu.mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !rw))
if ((state->mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
((state->mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !rw))
{
if (!pload)
{
MMULOG(("%s: set buserror (SR %04X)\n", __func__, m68ki_cpu.mmu_tmp_sr));
MMULOG(("%s: set buserror (SR %04X)\n", __func__, state->mmu_tmp_sr));
pmmu_set_buserror(state, addr_in);
}
}
@@ -634,7 +634,7 @@ uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8
{
pmmu_atc_add(state, addr_in, addr_out, fc, rw && type != 1);
}
MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, m68ki_cpu.mmu_tmp_sr));
MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, state->mmu_tmp_sr));
return addr_out;
}
@@ -645,20 +645,20 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
uint32 addr_out, tt0, tt1;
addr_out = addr_in;
m68ki_cpu.mmu_tmp_sr = 0;
state->mmu_tmp_sr = 0;
// transparent translation registers are always in force even if the PMMU itself is disabled
// they don't do much in emulation because we never write out of order, but the write-protect and cache control features
// are emulatable, and apparently transparent translation regions skip the page table lookup.
if (fc & 1) // data, use DTT0/DTT1
{
tt0 = m68ki_cpu.mmu_dtt0;
tt1 = m68ki_cpu.mmu_dtt1;
tt0 = state->mmu_dtt0;
tt1 = state->mmu_dtt1;
}
else if (fc & 2) // program, use ITT0/ITT1
{
tt0 = m68ki_cpu.mmu_itt0;
tt1 = m68ki_cpu.mmu_itt1;
tt0 = state->mmu_itt0;
tt1 = state->mmu_itt1;
}
else
{
@@ -676,7 +676,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
if ((addr_in & mask) == (tt0 & mask) && (fc & fcmask[(tt0 >> 13) & 3]) == fcmatch[(tt0 >> 13) & 3])
{
MMULOG(("TT0 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt0, mask));
if ((tt0 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
if ((tt0 & 4) && !state->mmu_tmp_rw && !ptest) // write protect?
{
pmmu_set_buserror(state, addr_in);
}
@@ -696,7 +696,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
if ((addr_in & mask) == (tt1 & mask) && (fc & fcmask[(tt1 >> 13) & 3]) == fcmatch[(tt1 >> 13) & 3])
{
MMULOG(("TT1 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt1, mask));
if ((tt1 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect?
if ((tt1 & 4) && !state->mmu_tmp_rw && !ptest) // write protect?
{
pmmu_set_buserror(state, addr_in);
}
@@ -705,7 +705,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
}
}
if (m68ki_cpu.pmmu_enabled)
if (state->pmmu_enabled)
{
uint32 root_idx = (addr_in >> 25) & 0x7f;
uint32 ptr_idx = (addr_in >> 18) & 0x7f;
@@ -716,11 +716,11 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
// select supervisor or user root pointer
if (fc & 4)
{
root_ptr = m68ki_cpu.mmu_srp_aptr + (root_idx<<2);
root_ptr = state->mmu_srp_aptr + (root_idx<<2);
}
else
{
root_ptr = m68ki_cpu.mmu_urp_aptr + (root_idx<<2);
root_ptr = state->mmu_urp_aptr + (root_idx<<2);
}
// get the root entry
@@ -739,7 +739,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
// PTEST: any write protect bits set in the search tree will set W in SR
if ((ptest) && (root_entry & 4))
{
m68ki_cpu.mmu_tmp_sr |= 4;
state->mmu_tmp_sr |= 4;
}
pointer_ptr = (root_entry & ~0x1ff) + (ptr_idx<<2);
@@ -748,7 +748,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
// PTEST: any write protect bits set in the search tree will set W in SR
if ((ptest) && (pointer_entry & 4))
{
m68ki_cpu.mmu_tmp_sr |= 4;
state->mmu_tmp_sr |= 4;
}
// update U bit on this pointer entry too
@@ -761,7 +761,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
MMULOG(("pointer entry = %08x\n", pointer_entry));
// write protected by the root or pointer entries?
if ((((root_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((pointer_entry & 4) && !m68ki_cpu.mmu_tmp_rw)) && !ptest)
if ((((root_entry & 4) && !state->mmu_tmp_rw) || ((pointer_entry & 4) && !state->mmu_tmp_rw)) && !ptest)
{
pmmu_set_buserror(state, addr_in);
return addr_in;
@@ -770,7 +770,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
// is UDT valid on the pointer entry?
if (!(pointer_entry & 2) && !ptest)
{
logerror("Invalid pointer entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in);
logerror("Invalid pointer entry! PC=%x, addr=%x\n", state->ppc, addr_in);
pmmu_set_buserror(state, addr_in);
return addr_in;
}
@@ -779,7 +779,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
}
else // throw an error
{
logerror("Invalid root entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in);
logerror("Invalid root entry! PC=%x, addr=%x\n", state->ppc, addr_in);
if (!ptest)
{
@@ -790,7 +790,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
}
// now do the page lookup
if (m68ki_cpu.mmu_tc & 0x4000) // 8k pages?
if (state->mmu_tc & 0x4000) // 8k pages?
{
page_idx = (addr_in >> 13) & 0x1f;
page = addr_in & 0x1fff;
@@ -807,7 +807,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
page_ptr = pointer_entry + (page_idx<<2);
page_entry = m68k_read_memory_32(page_ptr);
m68ki_cpu.mmu_last_page_entry_addr = page_ptr;
state->mmu_last_page_entry_addr = page_ptr;
MMULOG(("page_entry = %08x\n", page_entry));
@@ -815,12 +815,12 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
while ((page_entry & 3) == 2)
{
page_entry = m68k_read_memory_32(page_entry & ~0x3);
m68ki_cpu.mmu_last_page_entry_addr = (page_entry & ~0x3);
state->mmu_last_page_entry_addr = (page_entry & ~0x3);
}
m68ki_cpu.mmu_last_page_entry = page_entry;
state->mmu_last_page_entry = page_entry;
// is the page write protected or supervisor protected?
if ((((page_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
if ((((page_entry & 4) && !state->mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest)
{
pmmu_set_buserror(state, addr_in);
return addr_in;
@@ -829,7 +829,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
switch (page_entry & 3)
{
case 0: // invalid
MMULOG(("Invalid page entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in));
MMULOG(("Invalid page entry! PC=%x, addr=%x\n", state->ppc, addr_in));
if (!ptest)
{
pmmu_set_buserror(state, addr_in);
@@ -839,7 +839,7 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
case 1:
case 3: // normal
if (m68ki_cpu.mmu_tc & 0x4000) // 8k pages?
if (state->mmu_tc & 0x4000) // 8k pages?
{
addr_out = (page_entry & ~0x1fff) | page;
}
@@ -853,23 +853,23 @@ uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, ui
page_entry |= 0x8; // always set the U bit
// if we're writing, the M bit comes into play
if (!m68ki_cpu.mmu_tmp_rw)
if (!state->mmu_tmp_rw)
{
page_entry |= 0x10; // set Modified
}
// if these updates resulted in a change, write the entry back where we found it
if (page_entry != m68ki_cpu.mmu_last_page_entry && !m_side_effects_disabled)
if (page_entry != state->mmu_last_page_entry && !m_side_effects_disabled)
{
m68ki_cpu.mmu_last_page_entry = page_entry;
m68k_write_memory_32(m68ki_cpu.mmu_last_page_entry_addr, m68ki_cpu.mmu_last_page_entry);
state->mmu_last_page_entry = page_entry;
m68k_write_memory_32(state->mmu_last_page_entry_addr, state->mmu_last_page_entry);
}
}
else
{
// page entry: UR G U1 U0 S CM CM M U W PDT
// SR: B G U1 U0 S CM CM M 0 W T R
m68ki_cpu.mmu_tmp_sr |= ((addr_out & ~0xfff) || (page_entry & 0x7f4));
state->mmu_tmp_sr |= ((addr_out & ~0xfff) || (page_entry & 0x7f4));
}
break;
@@ -888,13 +888,13 @@ uint32 pmmu_translate_addr(m68ki_cpu_core *state, uint32 addr_in, uint16 rw)
{
uint32 addr_out;
if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
addr_out = pmmu_translate_addr_with_fc_040(state, addr_in, m68ki_cpu.mmu_tmp_fc, 0);
addr_out = pmmu_translate_addr_with_fc_040(state, addr_in, state->mmu_tmp_fc, 0);
}
else
{
addr_out = pmmu_translate_addr_with_fc(state, addr_in, m68ki_cpu.mmu_tmp_fc, rw, 7, 0, 0);
addr_out = pmmu_translate_addr_with_fc(state, addr_in, state->mmu_tmp_fc, rw, 7, 0, 0);
MMULOG(("ADDRIN %08X, ADDROUT %08X\n", addr_in, addr_out));
}
return addr_out;
@@ -904,15 +904,15 @@ int fc_from_modes(m68ki_cpu_core *state, uint16 modes)
{
if ((modes & 0x1f) == 0)
{
return m68ki_cpu.sfc;
return state->sfc;
}
if ((modes & 0x1f) == 1)
{
return m68ki_cpu.dfc;
return state->dfc;
}
if (m68ki_cpu.cpu_type & CPU_TYPE_030)
if (state->cpu_type & CPU_TYPE_030)
{
// 68030 has 3 bits fc, but 68851 4 bits
if (((modes >> 3) & 3) == 1)
@@ -952,9 +952,9 @@ void m68851_pload(m68ki_cpu_core *state, uint32 ea, uint16 modes)
MMULOG(("%s: PLOAD%c addr=%08x, fc=%d\n", __func__, rw ? 'R' : 'W', ltmp, fc));
// MC68851 traps if MMU is not enabled, 030 not
if (m68ki_cpu.pmmu_enabled || (m68ki_cpu.cpu_type & CPU_TYPE_030))
if (state->pmmu_enabled || (state->cpu_type & CPU_TYPE_030))
{
if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
pmmu_translate_addr_with_fc_040(state, ltmp, fc, 0);
}
@@ -981,10 +981,10 @@ void m68851_ptest(m68ki_cpu_core *state, uint32 ea, uint16 modes)
int fc = fc_from_modes(state, modes);
MMULOG(("PMMU: PTEST%c (%04X) pc=%08x sp=%08x va=%08x fc=%x level=%x a=%d, areg=%d\n",
rw ? 'R' : 'W', modes, m68ki_cpu.ppc, REG_A[7], v_addr, fc, level,
rw ? 'R' : 'W', modes, state->ppc, REG_A[7], v_addr, fc, level,
(modes & 0x100) ? 1 : 0, (modes >> 5) & 7));
if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type))
if (CPU_TYPE_IS_040_PLUS(state->cpu_type))
{
p_addr = pmmu_translate_addr_with_fc_040(state, v_addr, fc, 1);
}
@@ -993,9 +993,9 @@ void m68851_ptest(m68ki_cpu_core *state, uint32 ea, uint16 modes)
p_addr = pmmu_translate_addr_with_fc(state, v_addr, fc, rw, level, 1, 0);
}
m68ki_cpu.mmu_sr = m68ki_cpu.mmu_tmp_sr;
state->mmu_sr = state->mmu_tmp_sr;
MMULOG(("PMMU: PTEST result: %04x pa=%08x\n", m68ki_cpu.mmu_sr, p_addr));
MMULOG(("PMMU: PTEST result: %04x pa=%08x\n", state->mmu_sr, p_addr));
if (modes & 0x100)
{
int areg = (modes >> 5) & 7;
@@ -1008,30 +1008,30 @@ void m68851_pmove_get(m68ki_cpu_core *state, uint32 ea, uint16 modes)
switch ((modes>>10) & 0x3f)
{
case 0x02: // transparent translation register 0
WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt0);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt0));
WRITE_EA_32(state, ea, state->mmu_tt0);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", state->ppc, state->mmu_tt0));
break;
case 0x03: // transparent translation register 1
WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt1);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt1));
WRITE_EA_32(state, ea, state->mmu_tt1);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", state->ppc, state->mmu_tt1));
break;
case 0x10: // translation control register
WRITE_EA_32(state, ea, m68ki_cpu.mmu_tc);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tc));
WRITE_EA_32(state, ea, state->mmu_tc);
MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", state->ppc, state->mmu_tc));
break;
case 0x12: // supervisor root pointer
WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr);
MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
WRITE_EA_64(state, ea, (uint64)state->mmu_srp_limit<<32 | (uint64)state->mmu_srp_aptr);
MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", state->ppc, state->mmu_srp_limit, state->mmu_srp_aptr));
break;
case 0x13: // CPU root pointer
WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr);
MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
WRITE_EA_64(state, ea, (uint64)state->mmu_crp_limit<<32 | (uint64)state->mmu_crp_aptr);
MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", state->ppc, state->mmu_crp_limit, state->mmu_crp_aptr));
break;
default:
logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68ki_cpu.pc);
logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, state->pc);
return;
}
@@ -1053,13 +1053,13 @@ void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
if (((modes >> 10) & 7) == 2)
{
MMULOG(("WRITE TT0 = 0x%08x\n", m68ki_cpu.mmu_tt0));
m68ki_cpu.mmu_tt0 = temp;
MMULOG(("WRITE TT0 = 0x%08x\n", state->mmu_tt0));
state->mmu_tt0 = temp;
}
else if (((modes >> 10) & 7) == 3)
{
MMULOG(("WRITE TT1 = 0x%08x\n", m68ki_cpu.mmu_tt1));
m68ki_cpu.mmu_tt1 = temp;
MMULOG(("WRITE TT1 = 0x%08x\n", state->mmu_tt1));
state->mmu_tt1 = temp;
}
break;
@@ -1073,37 +1073,37 @@ void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
/* no break */
case 1:
logerror("680x0: unknown PMOVE case 1, PC %x\n", m68ki_cpu.pc);
logerror("680x0: unknown PMOVE case 1, PC %x\n", state->pc);
break;
case 2:
switch ((modes >> 10) & 7)
{
case 0: // translation control register
m68ki_cpu.mmu_tc = READ_EA_32(state, ea);
MMULOG(("PMMU: TC = %08x\n", m68ki_cpu.mmu_tc));
state->mmu_tc = READ_EA_32(state, ea);
MMULOG(("PMMU: TC = %08x\n", state->mmu_tc));
if (m68ki_cpu.mmu_tc & 0x80000000)
if (state->mmu_tc & 0x80000000)
{
int bits = 0;
for (int shift = 20; shift >= 0; shift -= 4)
{
bits += (m68ki_cpu.mmu_tc >> shift) & 0x0f;
bits += (state->mmu_tc >> shift) & 0x0f;
}
if (bits != 32 || !((m68ki_cpu.mmu_tc >> 23) & 1))
if (bits != 32 || !((state->mmu_tc >> 23) & 1))
{
logerror("MMU: TC invalid!\n");
m68ki_cpu.mmu_tc &= ~0x80000000;
state->mmu_tc &= ~0x80000000;
m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
} else {
m68ki_cpu.pmmu_enabled = 1;
state->pmmu_enabled = 1;
}
MMULOG(("PMMU enabled\n"));
}
else
{
m68ki_cpu.pmmu_enabled = 0;
state->pmmu_enabled = 0;
MMULOG(("PMMU disabled\n"));
}
@@ -1115,11 +1115,11 @@ void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
case 2: // supervisor root pointer
temp64 = READ_EA_64(state, ea);
m68ki_cpu.mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
m68ki_cpu.mmu_srp_aptr = temp64 & 0xffffffff;
MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr));
state->mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
state->mmu_srp_aptr = temp64 & 0xffffffff;
MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", state->mmu_srp_limit, state->mmu_srp_aptr));
// SRP type 0 is not allowed
if ((m68ki_cpu.mmu_srp_limit & 3) == 0)
if ((state->mmu_srp_limit & 3) == 0)
{
m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
return;
@@ -1133,11 +1133,11 @@ void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
case 3: // CPU root pointer
temp64 = READ_EA_64(state, ea);
m68ki_cpu.mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
m68ki_cpu.mmu_crp_aptr = temp64 & 0xffffffff;
MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr));
state->mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
state->mmu_crp_aptr = temp64 & 0xffffffff;
MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", state->mmu_crp_limit, state->mmu_crp_aptr));
// CRP type 0 is not allowed
if ((m68ki_cpu.mmu_crp_limit & 3) == 0)
if ((state->mmu_crp_limit & 3) == 0)
{
m68ki_exception_trap(state, EXCEPTION_MMU_CONFIGURATION);
return;
@@ -1150,14 +1150,14 @@ void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
break;
case 7: // MC68851 Access Control Register
if (m68ki_cpu.cpu_type == CPU_TYPE_020)
if (state->cpu_type == CPU_TYPE_020)
{
// DomainOS on Apollo DN3000 will only reset this to 0
uint16 mmu_ac = READ_EA_16(state, ea);
if (mmu_ac != 0)
{
MMULOG(("680x0 PMMU: pc=%x PMOVE to mmu_ac=%08x\n",
m68ki_cpu.ppc, mmu_ac));
state->ppc, mmu_ac));
}
break;
}
@@ -1165,14 +1165,14 @@ void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes)
/* fall through */
/* no break */
default:
logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68ki_cpu.pc);
logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, state->pc);
break;
}
break;
case 3: // MMU status
{
uint32 temp = READ_EA_32(state, ea);
logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68ki_cpu.pc);
logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, state->pc);
}
break;
}
@@ -1198,18 +1198,18 @@ void m68851_pmove(m68ki_cpu_core *state, uint32 ea, uint16 modes)
case 3: // MC68030 to/from status reg
if (modes & 0x200)
{
MMULOG(("%s: read SR = %04x\n", __func__, m68ki_cpu.mmu_sr));
WRITE_EA_16(state, ea, m68ki_cpu.mmu_sr);
MMULOG(("%s: read SR = %04x\n", __func__, state->mmu_sr));
WRITE_EA_16(state, ea, state->mmu_sr);
}
else
{
m68ki_cpu.mmu_sr = READ_EA_16(state, ea);
MMULOG(("%s: write SR = %04X\n", __func__, m68ki_cpu.mmu_sr));
state->mmu_sr = READ_EA_16(state, ea);
MMULOG(("%s: write SR = %04X\n", __func__, state->mmu_sr));
}
break;
default:
logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes >> 13) & 0x7, modes, m68ki_cpu.pc);
logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes >> 13) & 0x7, modes, state->pc);
break;
}
@@ -1219,27 +1219,27 @@ void m68851_pmove(m68ki_cpu_core *state, uint32 ea, uint16 modes)
void m68851_mmu_ops(m68ki_cpu_core *state)
{
uint16 modes;
uint32 ea = m68ki_cpu.ir & 0x3f;
uint32 ea = state->ir & 0x3f;
// catch the 2 "weird" encodings up front (PBcc)
if ((m68ki_cpu.ir & 0xffc0) == 0xf0c0)
if ((state->ir & 0xffc0) == 0xf0c0)
{
logerror("680x0: unhandled PBcc\n");
return;
}
else if ((m68ki_cpu.ir & 0xffc0) == 0xf080)
else if ((state->ir & 0xffc0) == 0xf080)
{
logerror("680x0: unhandled PBcc\n");
return;
}
else if ((m68ki_cpu.ir & 0xffe0) == 0xf500)
else if ((state->ir & 0xffe0) == 0xf500)
{
MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, m68ki_cpu.ir, (m68ki_cpu.ir >> 3) & 3, m68ki_cpu.ir & 7));
MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, state->ir, (state->ir >> 3) & 3, state->ir & 7));
pmmu_atc_flush(state);
}
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
{
switch ((m68ki_cpu.ir>>9) & 0x7)
switch ((state->ir>>9) & 0x7)
{
case 0:
modes = OPER_I_16(state);
@@ -1281,7 +1281,7 @@ void m68851_mmu_ops(m68ki_cpu_core *state)
break;
default:
logerror("680x0: unknown PMMU instruction group %d\n", (m68ki_cpu.ir>>9) & 0x7);
logerror("680x0: unknown PMMU instruction group %d\n", (state->ir>>9) & 0x7);
break;
}
}
@@ -1297,11 +1297,11 @@ inline uint32 hmmu_translate_addr(uint32 addr_in)
addr_out = addr_in;
// check if LC 24-bit mode is enabled - this simply blanks out A31, the V8 ignores A30-24 always
if (m68ki_cpu.hmmu_enabled == M68K_HMMU_ENABLE_LC)
if (state->hmmu_enabled == M68K_HMMU_ENABLE_LC)
{
addr_out = addr_in & 0xffffff;
}
else if (m68ki_cpu.hmmu_enabled == M68K_HMMU_ENABLE_II) // the original II does a more complex translation
else if (state->hmmu_enabled == M68K_HMMU_ENABLE_II) // the original II does a more complex translation
{
addr_out = addr_in & 0xffffff;
@@ -1328,19 +1328,19 @@ inline uint32 hmmu_translate_addr(uint32 addr_in)
int m68851_buserror(u32& addr)
{
if (!m68ki_cpu.pmmu_enabled)
if (!state->pmmu_enabled)
{
return false;
}
if (m68ki_cpu.mmu_tablewalk)
if (state->mmu_tablewalk)
{
MMULOG(("buserror during table walk\n"));
m68ki_cpu.mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
state->mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
return true;
}
addr = m68ki_cpu.mmu_last_logical_addr;
addr = state->mmu_last_logical_addr;
return false;
}
*/