mirror of
https://github.com/captain-amygdala/pistorm.git
synced 2026-02-11 02:30:03 +00:00
Various (some unused) GPIO things
This commit is contained in:
@@ -195,6 +195,7 @@ noppers:
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void *cpu_task() {
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m68ki_cpu_core *state = &m68ki_cpu;
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state->ovl = ovl;
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state->gpio = gpio;
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m68k_pulse_reset(state);
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cpu_loop:
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@@ -11,6 +11,7 @@
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#include <stddef.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <sys/mman.h>
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#include <sys/stat.h>
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#include <sys/types.h>
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@@ -153,6 +154,8 @@ void ps_write_32(unsigned int address, unsigned int value) {
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ps_write_16(address + 2, value);
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}
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#define NOP asm("nop"); asm("nop");
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unsigned int ps_read_16(unsigned int address) {
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*(gpio + 0) = GPFSEL0_OUTPUT;
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*(gpio + 1) = GPFSEL1_OUTPUT;
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@@ -219,9 +222,7 @@ unsigned int ps_read_8(unsigned int address) {
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}
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unsigned int ps_read_32(unsigned int address) {
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unsigned int a = ps_read_16(address);
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unsigned int b = ps_read_16(address + 2);
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return (a << 16) | b;
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return (ps_read_16(address) << 16) | ps_read_16(address + 2);
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}
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void ps_write_status_reg(unsigned int value) {
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@@ -63,6 +63,99 @@
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#define GPFSEL1_OUTPUT 0x09249249
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#define GPFSEL2_OUTPUT 0x00000249
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#define GPFSEL_OUTPUT \
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*(gpio + 0) = GPFSEL0_OUTPUT; \
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*(gpio + 1) = GPFSEL1_OUTPUT; \
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*(gpio + 2) = GPFSEL2_OUTPUT;
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#define GPFSEL_INPUT \
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*(gpio + 0) = GPFSEL0_INPUT; \
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*(gpio + 1) = GPFSEL1_INPUT; \
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*(gpio + 2) = GPFSEL2_INPUT;
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#define GPIO_WRITEREG(reg, val) \
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*(gpio + 7) = (val << 8) | (reg << PIN_A0); \
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*(gpio + 7) = 1 << PIN_WR; \
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*(gpio + 10) = 1 << PIN_WR; \
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*(gpio + 10) = 0xFFFFEC;
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#define GPIO_PIN_RD \
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*(gpio + 7) = (REG_DATA << PIN_A0); \
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*(gpio + 7) = 1 << PIN_RD;
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#define WAIT_TXN \
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while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS)) {}
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#define END_TXN \
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*(gpio + 10) = 0xFFFFEC;
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static inline void ps_write_8_ex(volatile uint32_t *gpio, uint32_t address, uint32_t data) {
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if (address & 0x01) {
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data &= 0xFF; // ODD , A0=1,LDS
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} else {
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data |= (data << 8); // EVEN, A0=0,UDS
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}
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GPFSEL_OUTPUT;
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GPIO_WRITEREG(REG_DATA, (data & 0xFFFF));
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GPIO_WRITEREG(REG_ADDR_LO, (address & 0xFFFF));
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GPIO_WRITEREG(REG_ADDR_HI, (0x0100 |(address >> 16)));
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GPFSEL_INPUT;
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WAIT_TXN;
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}
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static inline void ps_write_16_ex(volatile uint32_t *gpio, uint32_t address, uint32_t data) {
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GPFSEL_OUTPUT;
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GPIO_WRITEREG(REG_DATA, (data & 0xFFFF));
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GPIO_WRITEREG(REG_ADDR_LO, (address & 0xFFFF));
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GPIO_WRITEREG(REG_ADDR_HI, (0x0000 |(address >> 16)));
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GPFSEL_INPUT;
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WAIT_TXN;
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}
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static inline uint32_t ps_read_8_ex(volatile uint32_t *gpio, uint32_t address) {
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GPFSEL_OUTPUT;
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GPIO_WRITEREG(REG_ADDR_LO, (address & 0xFFFF));
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GPIO_WRITEREG(REG_ADDR_HI, (0x0300 |(address >> 16)));
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asm("nop"); asm("nop");
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GPFSEL_INPUT;
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GPIO_PIN_RD;
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WAIT_TXN;
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uint32_t value = ((*(gpio + 13) >> 8) & 0xFFFF);
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END_TXN;
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if (address & 0x01)
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return value & 0xff; // ODD , A0=1,LDS
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else
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return (value >> 8); // EVEN, A0=0,UDS
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}
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static inline uint32_t ps_read_16_ex(volatile uint32_t *gpio, uint32_t address) {
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GPFSEL_OUTPUT;
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GPIO_WRITEREG(REG_ADDR_LO, (address & 0xFFFF));
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GPIO_WRITEREG(REG_ADDR_HI, (0x0200 |(address >> 16)));
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asm("nop"); asm("nop");
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GPFSEL_INPUT;
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GPIO_PIN_RD;
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WAIT_TXN;
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uint32_t value = ((*(gpio + 13) >> 8) & 0xFFFF);
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END_TXN;
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return value;
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}
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unsigned int ps_read_8(unsigned int address);
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unsigned int ps_read_16(unsigned int address);
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unsigned int ps_read_32(unsigned int address);
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@@ -88,6 +181,16 @@ unsigned int ps_get_ipl_zero();
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#define write16 ps_write_16
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#define write32 ps_write_32
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static inline void ps_write_32_ex(volatile uint32_t *gpio, uint32_t address, uint32_t data) {
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ps_write_16_ex(gpio, address, data >> 16);
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ps_write_16_ex(gpio, address + 2, data);
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}
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static inline uint32_t ps_read_32_ex(volatile uint32_t *gpio, uint32_t address) {
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return (ps_read_16_ex(gpio, address) << 16) | ps_read_16_ex(gpio, address + 2);
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}
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#define write_reg ps_write_status_reg
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#define read_reg ps_read_status_reg
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