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Code Issues Projects Releases Wiki Activity
593 Commits 4 Branches 0 Tags
48c66af00d28ecdb205f70e4eaffd7a2cc493b9c
Commit Graph

9 Commits

Author SHA1 Message Date
Marcus Agehall
36afc41b13 Added support for C1/C3 clock calculation 2021-10-14 16:52:12 +02:00
Your Name
b28ea5130b Experimental MaxV support added. This is very alpha and likely makes problems 2021-07-17 11:57:37 +01:00
beeanyew
bab7a847c0 Make experimental bitstream optional 2021-06-20 16:59:11 +01:00
shanshe
d602910beb Improve 68k cycle state machine 
S7 and S0 states are made faster to gain almost a c7m cycle, making Chip
access faster. (sysinfo 4.4 chip speed from 0.97 to 1.13)
 2021-06-18 11:48:45 +02:00
beeanyew
15fdee25f5 Make rtl/make.bat not anger people unnecessarily 2021-05-13 09:27:36 +02:00
shanshe
75bbc70be8 Reset from Amiga CTRL+A+A 2021-04-13 21:53:44 +02:00
beeanyew
f554e207a4 Update readme(s) and Hardware files 2021-04-08 14:00:30 +02:00
beeanyew
1f804c7e36 [WIP] IRQ experiments, revert Musashi speed hax for now 2021-03-08 15:53:23 +01:00
beeanyew
e764148bb1 [WIP] Pile of stuff 
PiSCSI Boot ROM progress, various fixes and enhancements, TD64 support
Added updated open source RTL and bit stream by Niklas Ekström (https://github.com/niklasekstrom)
 2021-02-10 08:33:52 +01:00