Initial commit

2026-02-01 06:22:46 +00:00 · 2021-05-18 12:55:49 +03:00
commit 531dcb2da5
18 changed files with 61600 additions and 0 deletions
--- a/glm_ucode_disasm/cregs.txt
+++ b/glm_ucode_disasm/cregs.txt
@@ -0,0 +1,16 @@
+067: CORE_CR_CUR_RIP
+068: CORE_CR_CUR_UIP
+285: CTAP_CR_DFX_CTL_STS
+288: UCODE_CR_X2APIC_TPR
+28b: UCODE_CR_X2APIC_EOI
+29f: UCODE_CR_PPPE_EVENT_STATUS
+2c4: ML3_CR_PIC_GLOBAL_EVENT_INHIBIT
+2df: ROB1_CR_ICECTLPMR
+528: PMH_CR_CR3
+572: PMH_CR_SMRR_BASE
+573: PMH_CR_SMRR_MASK
+574: PMH_CR_EMRR_BASE
+575: PMH_CR_EMRR_MASK
+7c5: CORE_CR_CR4
+7f6: CORE_CR_CR0
+7fe: CORE_CR_EFLAGS
--- a/glm_ucode_disasm/fscp.txt
+++ b/glm_ucode_disasm/fscp.txt
@@ -0,0 +1 @@
+003a: FSCP_CR_IA32_FEATURE_CTL
--- a/glm_ucode_disasm/glm_ucode_disasm.py
+++ b/glm_ucode_disasm/glm_ucode_disasm.py
--- a/glm_ucode_disasm/hard_imm.txt
+++ b/glm_ucode_disasm/hard_imm.txt
--- a/glm_ucode_disasm/idq_test_imms.txt
+++ b/glm_ucode_disasm/idq_test_imms.txt
@@ -0,0 +1,8 @@
+0000000000000002 0000000000003ffc 0000000000000068 0000000000000001
+000000000000001f 000000000000000e 0000000000000030 0000000000000000
+0000000000000000 0000000000000000 0000000000000004 0000000000000000
+0000000000020000 0000000000008000 0000000000000000 00000000000022df
+0000000000000021 0000000000000000 000000000000000d 0000000002000000
+0000000000000000 0000000000040000 0000000020000000 0000000000000000
+000000000000001f 0000000000800000 0000000000000000 000000000000003a
+0000000000080001 0000000000400000 ffffffffffff20a5 0000000000000001
--- a/glm_ucode_disasm/idq_test_uops.txt
+++ b/glm_ucode_disasm/idq_test_uops.txt
@@ -0,0 +1,8 @@
+06beccefe0d40f0e 0000008000200002 001880800007c002 0002008000240002
+0005488200040002 0018c08000044002 0019488220044002 03774c4840100b02
+00300c0800100b02 00300c0800100b02 000c888200040002 00004cc600244002
+001104dc00240002 004c088200040002 00004cc600244002 001880800004c202
+00194882e0040002 00004cc260240002 0005088200040002 000c888200040102
+00004cc600244002 000104dc00240002 004c488200040102 00004cc600244002
+00194882e0040002 0001c88200240102 00004cc600244002 0018c08000040002
+0001c88200240002 004c488200040102 001880800007c002 001880800007c002
--- a/glm_ucode_disasm/lables.txt
+++ b/glm_ucode_disasm/lables.txt
@@ -0,0 +1,80 @@
+0011: sha256_ret
+02d8: sidt_xlat
+0320: vmresume_xlat
+0328: vmlaunch_xlat
+0330: vmwrite_r64_mem_xlat
+0428: rdrand_xlat
+0430: rdseed_xlat
+04ae: set_carry_uend
+0660: udbgwr_xlat
+06be: jump_tmp3
+06c6: uret1
+0720: sldt_m16_xlat
+0738: sysexit_xlat
+0788: rdtscp_xlat
+0794: clear_aflags_uend0
+0818: hlt_xlat
+0890: mov_cr0_r64_xlat
+08c0: rsm_xlat
+08c8: vmxoff_xlat
+08d0: encls_xlat
+0a68: sldt_r16_xlat
+0ae0: rdmsr_xlat
+0ae8: vmxon_xlat
+0af0: vmptrld_xlat
+0af8: vmclear_xlat
+0b08: vmcall_xlat
+0b10: enclu_xlat
+0b58: udbgrd_xlat
+0b90: lidt_xlat
+0ba0: str_m16_xlat
+0bc9: write_port_4c
+0bd0: wmptrst_xlat
+0be0: cpuid_xlat
+0c10: sgdt_xlat
+0c70: mov_r64_cr8_xlat
+0c80: wrmsr_xlat
+0ca8: rdtsc_xlat
+0cc0: rdpmc_xlat
+0cd8: vmwrite_r64_r64_xlat
+17ec: uend
+1861: rdrand_impl
+1cbe: uret1
+1d8d: check_rdrand_vmexits
+1ea6: patch_runs_load_loop
+1f90: do_smm_vmexit
+1f91: do_smm_vmexit_ovr_enter_rip
+2711: generate_#GP
+2769: generate_#UD
+2771: generate_#NM
+27b4: patch_load_error
+27c1: uarch_bufs_ldat_init
+27f1: patch_apply_error
+2d72: check_rsa_padding_signature
+2b15: lbsync_full
+304e: uret0
+3210: uend0
+327c: apply_ucode_patch
+35a5: exit_probe_mode
+3a41: enter_probe_mode
+3dfa: check_cpl_uend3
+44f9: probe_mode_force_sgx_eenter_eresume
+4000: reset_flow
+4644: check_rsa_pub_key_hash
+465c: gen_rc4_key
+4e81: do_vmexit
+4e82: do_vmexit_ovr_enter_rip
+50c4: calc_sha256_start
+50da: calc_sha256_update
+556a: calc_fast_sha256_start
+5795: rsa_signing_error
+5c01: probe_mode_force_smm_xlat
+5e68: fit_process_error
+5ed5: rc4_decrypt
+608a: fit_load_end
+64ea: ucode_fit_xlat_found
+6e16: fit_load_start
+6e42: process_next_fit_xlat
+6e4c: non_ucode_fit_xlat_found
+735c: rsa_decrypt
+75c6: enclu_impl
--- a/glm_ucode_disasm/opcodes.txt
+++ b/glm_ucode_disasm/opcodes.txt
@@ -0,0 +1,641 @@
+000: ADD_DSZ32
+001: OR_DSZ32
+004: AND_DSZ32
+005: SUB_DSZ32
+006: XOR_DSZ32
+007: NOTAND_DSZ32
+008: ZEROEXT_DSZ32
+009: MOVE_DSZ32
+00a: TESTUSTATE
+00b: UPDATEUSTATE
+00c: SAVEUIP
+00d: SAVEUIP_REGOVR
+00e: WRMSLOOPCTRFBR
+014: BT_DSZ32
+015: BTS_DSZ32
+016: BTR_DSZ32
+017: BTC_DSZ32
+01e: MJMPTARGET_INDIRECT_ASZ32
+021: CONCAT_DSZ32
+024: SHL_DSZ32
+025: SHR_DSZ32
+02c: ROL_DSZ32
+02d: ROR_DSZ32
+02e: SAR_DSZ32
+030: SELECTCC_DSZ32_CONDO
+031: SELECTCC_DSZ32_CONDNO
+032: SELECTCC_DSZ32_CONDB
+033: SELECTCC_DSZ32_CONDNB
+034: CMOVCC_DSZ32_CONDO
+035: CMOVCC_DSZ32_CONDNO
+036: CMOVCC_DSZ32_CONDB
+037: CMOVCC_DSZ32_CONDNB
+03d: MOVEINSERTFLGS_DSZ32
+040: ADD_DSZ64
+041: OR_DSZ64
+042: MOVETOCREG_DSZ64
+043: WRITEURAM
+044: AND_DSZ64
+045: SUB_DSZ64
+046: XOR_DSZ64
+047: NOTAND_DSZ64
+048: ZEROEXT_DSZ64
+049: MOVE_DSZ64
+04a: TESTUSTATE
+04c: SAVEUIP
+050: UJMPCC_DIRECT_NOTTAKEN_CONDO
+051: UJMPCC_DIRECT_NOTTAKEN_CONDNO
+052: UJMPCC_DIRECT_NOTTAKEN_CONDB
+053: UJMPCC_DIRECT_NOTTAKEN_CONDNB
+054: BT_DSZ64
+055: BTS_DSZ64
+056: BTR_DSZ64
+057: BTC_DSZ64
+058: MJMPCC_DSZNOP_CONDO
+059: MJMPCC_DSZNOP_CONDNO
+05a: MJMPCC_DSZNOP_CONDB
+05b: MJMPCC_DSZNOP_CONDNB
+05c: MJMPTARGET_INDIRECT_ASZ64
+05e: MJMPTARGET_INDIRECT_ASZ64
+062: MOVEFROMCREG_DSZ64
+063: READURAM
+064: SHL_DSZ64
+065: SHR_DSZ64
+06c: ROL_DSZ64
+06d: ROR_DSZ64
+06e: SAR_DSZ64
+070: SELECTCC_DSZ64_CONDO
+071: SELECTCC_DSZ64_CONDNO
+072: SELECTCC_DSZ64_CONDB
+073: SELECTCC_DSZ64_CONDNB
+074: CMOVCC_DSZ64_CONDO
+075: CMOVCC_DSZ64_CONDNO
+076: CMOVCC_DSZ64_CONDB
+077: CMOVCC_DSZ64_CONDNB
+07d: MOVEINSERTFLGS_DSZ64
+080: ADD_DSZ16
+081: OR_DSZ16
+084: AND_DSZ16
+085: SUB_DSZ16
+086: XOR_DSZ16
+087: NOTAND_DSZ16
+088: ZEROEXT_DSZ16
+08c: SAVEUIP
+094: BT_DSZ16
+095: BTS_DSZ16
+096: BTR_DSZ16
+097: BTC_DSZ16
+0a1: CONCAT_DSZ16
+0a4: SHL_DSZ16
+0a5: SHR_DSZ16
+0a8: MOVSX_DSZ16
+0a9: MOVZX_DSZ16
+0ac: ROL_DSZ16
+0ad: ROR_DSZ16
+0ae: SAR_DSZ16
+0b4: CMOVCC_DSZ16_CONDO
+0b5: CMOVCC_DSZ16_CONDNO
+0b6: CMOVCC_DSZ16_CONDB
+0b7: CMOVCC_DSZ16_CONDNB
+0c0: ADD_DSZ8
+0c1: OR_DSZ8
+0c4: AND_DSZ8
+0c5: SUB_DSZ8
+0c6: XOR_DSZ8
+0c7: NOTAND_DSZ8
+0c8: ZEROEXT_DSZ8
+0cc: SAVEUIP
+0e0: NEG_DSZ8
+0e1: CONCAT_DSZ8
+0e4: SHL_DSZ8
+0e5: SHR_DSZ8
+0e8: MOVSX_DSZ8
+0e9: MOVZX_DSZ8
+0ec: ROL_DSZ8
+0ed: ROR_DSZ8
+0ee: SAR_DSZ8
+0f4: CMOVCC_DSZ8_CONDO
+0f5: CMOVCC_DSZ8_CONDNO
+0f6: CMOVCC_DSZ8_CONDB
+0f7: CMOVCC_DSZ8_CONDNB
+0f8: SETCC_CONDO
+0f9: SETCC_CONDNO
+0fa: SETCC_CONDB
+0fb: SETCC_CONDNB
+108: READUIP_REGOVR
+120: SUBR_DSZ32
+122: RCXBTCNTMSK_DSZ32
+130: SELECTCC_DSZ32_CONDZ
+131: SELECTCC_DSZ32_CONDNZ
+132: SELECTCC_DSZ32_CONDBE
+133: SELECTCC_DSZ32_CONDNBE
+134: CMOVCC_DSZ32_CONDZ
+135: CMOVCC_DSZ32_CONDNZ
+136: CMOVCC_DSZ32_CONDBE
+137: CMOVCC_DSZ32_CONDNBE
+13e: MOVEMERGEFLGS_DSZ32
+142: UFLOWCTRL
+143: AETTRACE
+148: URET
+150: UJMPCC_DIRECT_NOTTAKEN_CONDZ
+151: UJMPCC_DIRECT_NOTTAKEN_CONDNZ
+152: UJMPCC_DIRECT_NOTTAKEN_CONDBE
+153: UJMPCC_DIRECT_NOTTAKEN_CONDNBE
+158: MJMPCC_DSZNOP_CONDZ
+159: MJMPCC_DSZNOP_CONDNZ
+15a: MJMPCC_DSZNOP_CONDBE
+15b: MJMPCC_DSZNOP_CONDNBE
+15d: UJMP
+15f: UJMPCC_DIRECT_TAKEN_CONDZ
+160: SUBR_DSZ64
+162: RCXBTCNTMSK_DSZ64
+170: SELECTCC_DSZ64_CONDZ
+171: SELECTCC_DSZ64_CONDNZ
+172: SELECTCC_DSZ64_CONDBE
+173: SELECTCC_DSZ64_CONDNBE
+174: CMOVCC_DSZ64_CONDZ
+175: CMOVCC_DSZ64_CONDNZ
+176: CMOVCC_DSZ64_CONDBE
+177: CMOVCC_DSZ64_CONDNBE
+17e: MOVEMERGEFLGS_DSZ64
+189: ADDSUB_DSZ16_CONDD
+1a0: SUBR_DSZ16
+1a2: RCXBTCNTMSK_DSZ16
+1b4: CMOVCC_DSZ16_CONDZ
+1b5: CMOVCC_DSZ16_CONDNZ
+1b6: CMOVCC_DSZ16_CONDBE
+1b7: CMOVCC_DSZ16_CONDNBE
+1bf: SAHF
+1e0: SUBR_DSZ8
+1e2: RCXBTCNTMSK_DSZ8
+1f4: CMOVCC_DSZ8_CONDZ
+1f5: CMOVCC_DSZ8_CONDNZ
+1f6: CMOVCC_DSZ8_CONDBE
+1f7: CMOVCC_DSZ8_CONDNBE
+1f8: SETCC_CONDZ
+1f9: SETCC_CONDNZ
+1fa: SETCC_CONDBE
+1fb: SETCC_CONDNBE
+202: PSELECT_CPL0
+214: FETCHFROMEIP0_ASZ32
+215: FETCHFROMEIP1_ASZ32
+21e: SIGEVENT
+225: IMUL32L_DSZ32
+228: MSR2CR
+22c: MUL_DSZ32
+22d: IMUL_DSZ32
+230: SELECTCC_DSZ32_CONDS
+231: SELECTCC_DSZ32_CONDNS
+232: SELECTCC_DSZ32_CONDP
+233: SELECTCC_DSZ32_CONDNP
+234: CMOVCC_DSZ32_CONDS
+235: CMOVCC_DSZ32_CONDNS
+236: CMOVCC_DSZ32_CONDP
+237: CMOVCC_DSZ32_CONDNP
+250: UJMPCC_DIRECT_NOTTAKEN_CONDS
+251: UJMPCC_DIRECT_NOTTAKEN_CONDNS
+252: UJMPCC_DIRECT_NOTTAKEN_CONDP
+253: UJMPCC_DIRECT_NOTTAKEN_CONDNP
+254: FETCHFROMEIP0_ASZ64
+255: FETCHFROMEIP1_ASZ64
+258: MJMPCC_DSZNOP_CONDS
+259: MJMPCC_DSZNOP_CONDNS
+25a: MJMPCC_DSZNOP_CONDP
+25b: MJMPCC_DSZNOP_CONDNP
+25d: TEST_DSZ64
+264: IMUL64L_DSZ64
+269: RDVMCSPLA
+270: SELECTCC_DSZ64_CONDS
+271: SELECTCC_DSZ64_CONDNS
+272: SELECTCC_DSZ64_CONDP
+273: SELECTCC_DSZ64_CONDNP
+274: CMOVCC_DSZ64_CONDS
+275: CMOVCC_DSZ64_CONDNS
+276: CMOVCC_DSZ64_CONDP
+277: CMOVCC_DSZ64_CONDNP
+2b4: CMOVCC_DSZ16_CONDS
+2b5: CMOVCC_DSZ16_CONDNS
+2b6: CMOVCC_DSZ16_CONDP
+2b7: CMOVCC_DSZ16_CONDNP
+2f4: CMOVCC_DSZ8_CONDS
+2f5: CMOVCC_DSZ8_CONDNS
+2f6: CMOVCC_DSZ8_CONDP
+2f7: CMOVCC_DSZ8_CONDNP
+2f8: SETCC_CONDS
+2f9: SETCC_CONDNS
+2fa: SETCC_CONDP
+2fb: SETCC_CONDNP
+32e: RCL_DSZ32
+330: SELECTCC_DSZ32_CONDL
+331: SELECTCC_DSZ32_CONDNL
+332: SELECTCC_DSZ32_CONDLE
+333: SELECTCC_DSZ32_CONDNLE
+334: CMOVCC_DSZ32_CONDL
+335: CMOVCC_DSZ32_CONDNL
+336: CMOVCC_DSZ32_CONDLE
+337: CMOVCC_DSZ32_CONDNLE
+338: CLC
+339: CMC
+33a: STC
+33c: BSWAP_DSZ32
+33e: ADC
+33f: SBB
+350: UJMPCC_DIRECT_NOTTAKEN_CONDL
+351: UJMPCC_DIRECT_NOTTAKEN_CONDNL
+352: UJMPCC_DIRECT_NOTTAKEN_CONDLE
+353: UJMPCC_DIRECT_NOTTAKEN_CONDNLE
+358: MJMPCC_DSZNOP_CONDL
+359: MJMPCC_DSZNOP_CONDNL
+35a: MJMPCC_DSZNOP_CONDLE
+35b: MJMPCC_DSZNOP_CONDNLE
+370: SELECTCC_DSZ64_CONDL
+371: SELECTCC_DSZ64_CONDNL
+372: SELECTCC_DSZ64_CONDLE
+373: SELECTCC_DSZ64_CONDNLE
+374: CMOVCC_DSZ64_CONDL
+375: CMOVCC_DSZ64_CONDNL
+376: CMOVCC_DSZ64_CONDLE
+377: CMOVCC_DSZ64_CONDNLE
+37d: GENARITHFLAGS
+380: READAFLAGS
+3ae: RCL_DSZ16
+3b4: CMOVCC_DSZ16_CONDL
+3b5: CMOVCC_DSZ16_CONDNL
+3b6: CMOVCC_DSZ16_CONDLE
+3b7: CMOVCC_DSZ16_CONDNLE
+3c0: LAHF
+3c8: INC_DSZ8
+3ca: DEC_DSZ8
+3ee: RCL_DSZ8
+3f4: CMOVCC_DSZ8_CONDL
+3f5: CMOVCC_DSZ8_CONDNL
+3f6: CMOVCC_DSZ8_CONDLE
+3f7: CMOVCC_DSZ8_CONDNLE
+3f8: SETCC_CONDL
+3f9: SETCC_CONDNL
+3fa: SETCC_CONDLE
+3fb: SETCC_CONDNLE
+3fe: ADC
+3ff: SBB
+440: PSUBSB
+441: PSUBSW
+442: PMINSW
+443: POR
+444: PADDSB
+445: PADDSW
+446: PMAXSW
+447: PXOR
+448: PSUBB
+449: PSUBW
+44a: PSUBD
+44c: PADDB
+44d: PADDW
+44e: PADDD
+450: PCMPGTB
+451: PCMPGTW
+452: PCMPGTD
+457: PALIGNR
+458: PCMPEQW
+459: PCMPEQB
+45a: PCMPEQD
+45b: PADDQ
+45f: PSUBQ
+460: PSUBUSB
+461: PSUBUSW
+462: PMINUB
+463: PAND
+464: PADDUSB
+465: PADDUSW
+466: PMAXUB
+467: PANDN
+468: PAVGB
+46b: PAVGW
+470: MOVLPD
+471: MOVHPD
+472: MOVDQU
+4b4: FMOV
+4c3: ORPD
+4c7: XORPD
+4e3: ANDPD
+4e7: ANDNPD
+4ef: MOVHLPS
+508: PUNPCKLDQ
+50a: PSRLQ
+50e: PSLLQ
+514: CVTPD2PI
+518: PUNPCKHDQ
+51a: PSRLQ
+51d: PACKSSDW
+51e: PSLLQ
+528: UNPCKHPD
+529: UNPCKLPD
+556: PMADDWD
+557: PSADBW
+571: CVTPD2PS
+588: PUNPCKLWD
+58a: PSRLD
+58c: PSRAD
+58e: PSLLD
+594: CVTTPD2PI
+598: PUNPCKHWD
+59a: PSRLD
+59b: PSHUFD
+59c: PSRAD
+59d: PACKSSWB
+59e: PSLLD
+59f: PACKUSWB
+5c8: PUNPCKLBW
+5ca: PSRLW
+5cc: PSRAW
+5ce: PSLLW
+5d8: PUNPCKHBW
+5da: PSRLW
+5dc: PSRAW
+5de: PSLLW
+5f3: CVTDQ2PS
+5f5: CVTPI2PD
+5f9: MOVUPD
+5fa: SHUFPD
+608: FADDP
+646: FDIV
+650: PMULUDQ
+652: PMULHUW
+654: PMULLW
+655: PMULHW
+685: FILD
+68a: FCOM2
+6f1: MULPD
+6f5: SQRTPD
+6f6: DIVPD
+6f8: ADDPD
+6fc: SUBPD
+6fd: MINPD
+6fe: CMPPD
+6ff: MAXPD
+705: PINTMOVDI2MM_DSZ32
+716: FPREADROM_DTYPENOP
+720: FCOMIP
+722: COMISD
+723: UCOMISD
+72c: PINTMOVDTMM2I_DSZ32
+72d: PINTMOVDMM2I_DSZ32
+745: PINTMOVDI2MM_DSZ64
+769: PMOVMSKB
+76c: PINTMOVDTMM2I_DSZ64
+76d: PINTMOVDMM2I_DSZ64
+785: PINSRW
+7ad: PEXTRW
+7b8: RSQRTPS
+7ed: FCMOVNE
+7f8: MOVMSKPD
+81f: LA2LIN_DSZ32
+822: MOVETOCREG_AND_DSZ64
+86a: BTUJB_DIRECT_NOTTAKEN
+86b: BTUJNB_DIRECT_NOTTAKEN
+89f: LA2LIN_DSZ64
+8a2: MOVETOCREG_SHL_DSZ64
+902: MOVETOCREG_OR_DSZ64
+928: CMPUJZ_DIRECT_NOTTAKEN
+929: CMPUJNZ_DIRECT_NOTTAKEN
+962: MOVETOCREG_BTS_DSZ64
+9a2: MOVETOCREG_SHR_DSZ64
+996: SHLD
+997: SHRD
+a62: MOVETOCREG_BTR_DSZ64
+c00: LDZX_DSZ32_ASZ32_SC1
+c03: LEA_DSZ32_ASZ32_SC1
+c08: STAD_DSZ32_ASZ32_SC1
+c09: STADTICKLE_DSZ32_ASZ32_SC1
+c0a: LDTICKLE_DSZ32_ASZ32_SC1
+c0e: MOVNTPD
+c10: LDZX_DSZ32_ASZ32_SC1
+c13: LEA_DSZ32_ASZ32_SC1
+c18: STAD_DSZ32_ASZ32_SC1
+c19: STADTICKLE_DSZ32_ASZ32_SC1
+c1a: LDTICKLE_DSZ32_ASZ32_SC1
+c2e: MOVHPD
+c30: LDZX_DSZ32_ASZ32_SC1
+c33: LEA_DSZ32_ASZ32_SC1
+c38: STAD_DSZ32_ASZ32_SC1
+c39: STADTICKLE_DSZ32_ASZ32_SC1
+c3a: LDTICKLE_DSZ32_ASZ32_SC1
+c40: LDZX_DSZ64_ASZ32_SC1
+c43: LEA_DSZ64_ASZ32_SC1
+c48: STAD_DSZ64_ASZ32_SC1
+c49: STADTICKLE_DSZ64_ASZ32_SC1
+c4a: LDTICKLE_DSZ64_ASZ32_SC1
+c4b: RDSEGFLD
+c50: LDZX_DSZ64_ASZ32_SC1
+c53: LEA_DSZ64_ASZ32_SC1
+c58: STAD_DSZ64_ASZ32_SC1
+c59: STADTICKLE_DSZ64_ASZ32_SC1
+c5a: LDTICKLE_DSZ64_ASZ32_SC1
+c5e: MOVLPD
+c6b: WRSEGFLD
+c70: LDZX_DSZ64_ASZ32_SC1
+c73: LEA_DSZ64_ASZ32_SC1
+c78: STAD_DSZ64_ASZ32_SC1
+c79: STADTICKLE_DSZ64_ASZ32_SC1
+c7a: LDTICKLE_DSZ64_ASZ32_SC1
+c7b: WRSEGFLD
+c80: LDZX_DSZ16_ASZ32_SC1
+c83: LEA_DSZ16_ASZ32_SC1
+c88: STAD_DSZ16_ASZ32_SC1
+c89: STADTICKLE_DSZ16_ASZ32_SC1
+c8a: LDTICKLE_DSZ16_ASZ32_SC1
+c90: LDZX_DSZ16_ASZ32_SC1
+c93: LEA_DSZ16_ASZ32_SC1
+c98: STAD_DSZ16_ASZ32_SC1
+c99: STADTICKLE_DSZ16_ASZ32_SC1
+c9a: LDTICKLE_DSZ16_ASZ32_SC1
+cb0: LDZX_DSZ16_ASZ32_SC1
+cb3: LEA_DSZ16_ASZ32_SC1
+cb8: STAD_DSZ16_ASZ32_SC1
+cb9: STADTICKLE_DSZ16_ASZ32_SC1
+cba: LDTICKLE_DSZ16_ASZ32_SC1
+cbe: MOVNTDQ
+cc0: LDZX_DSZ8_ASZ32_SC1
+ccf: LEA_DSZ8_ASZ32_SC1
+cc8: STAD_DSZ8_ASZ32_SC1
+cc9: STADTICKLE_DSZ8_ASZ32_SC1
+cca: LDTICKLE_DSZ8_ASZ32_SC1
+cd0: LDZX_DSZ8_ASZ32_SC1
+cd3: LEA_DSZ8_ASZ32_SC1
+cd8: STAD_DSZ8_ASZ32_SC1
+cd9: STADTICKLE_DSZ8_ASZ32_SC1
+cda: LDTICKLE_DSZ8_ASZ32_SC1
+cf0: LDZX_DSZ8_ASZ32_SC1
+cf3: LEA_DSZ8_ASZ32_SC1
+cf5: LDHINT_BUFFER_ASZ32_SC1
+cf8: STAD_DSZ8_ASZ32_SC1
+cf9: STADTICKLE_DSZ8_ASZ32_SC1
+cfa: LDTICKLE_DSZ8_ASZ32_SC1
+cfe: MASKMOVDQU
+d00: LDZX_DSZ32_ASZ32_SC4
+d03: LEA_DSZ32_ASZ32_SC4
+d08: STAD_DSZ32_ASZ32_SC4
+d09: STADTICKLE_DSZ32_ASZ32_SC4
+d0a: LDTICKLE_DSZ32_ASZ32_SC4
+d0b: PORTIN_DSZ32_ASZ16_SC1
+d0f: PORTOUT_DSZ32_ASZ16_SC1
+d10: LDZX_DSZ32_ASZ32_SC4
+d13: LEA_DSZ32_ASZ32_SC4
+d18: STAD_DSZ32_ASZ32_SC4
+d19: STADTICKLE_DSZ32_ASZ32_SC4
+d1a: LDTICKLE_DSZ32_ASZ32_SC4
+d30: LDZX_DSZ32_ASZ32_SC1
+d33: LEA_DSZ32_ASZ32_SC1
+d38: STAD_DSZ32_ASZ32_SC1
+d39: STADTICKLE_DSZ32_ASZ32_SC1
+d3a: LDTICKLE_DSZ32_ASZ32_SC1
+d40: LDZX_DSZ64_ASZ32_SC4
+d43: LEA_DSZ64_ASZ32_SC4
+d48: STAD_DSZ64_ASZ32_SC4
+d49: STADTICKLE_DSZ64_ASZ32_SC4
+d4a: LDTICKLE_DSZ64_ASZ32_SC4
+d4b: PORTIN_DSZ64_ASZ16_SC1
+d4f: PORTOUT_DSZ64_ASZ16_SC1
+d50: LDZX_DSZ64_ASZ32_SC4
+d53: LEA_DSZ64_ASZ32_SC4
+d58: STAD_DSZ64_ASZ32_SC4
+d59: STADTICKLE_DSZ64_ASZ32_SC4
+d5a: LDTICKLE_DSZ64_ASZ32_SC4
+d70: LDZX_DSZ64_ASZ32_SC1
+d73: LEA_DSZ64_ASZ32_SC1
+d78: STAD_DSZ64_ASZ32_SC1
+d79: STADTICKLE_DSZ64_ASZ32_SC1
+d7a: LDTICKLE_DSZ64_ASZ32_SC1
+d80: LDZX_DSZ16_ASZ32_SC4
+d83: LEA_DSZ16_ASZ32_SC4
+d88: STAD_DSZ16_ASZ32_SC4
+d89: STADTICKLE_DSZ16_ASZ32_SC4
+d8a: LDTICKLE_DSZ16_ASZ32_SC4
+d8b: PORTIN_DSZ16_ASZ16_SC1
+d8f: PORTOUT_DSZ16_ASZ16_SC1
+d90: LDZX_DSZ16_ASZ32_SC4
+d93: LEA_DSZ16_ASZ32_SC4
+d98: STAD_DSZ16_ASZ32_SC4
+d99: STADTICKLE_DSZ16_ASZ32_SC4
+d9a: LDTICKLE_DSZ16_ASZ32_SC4
+db0: LDZX_DSZ16_ASZ32_SC1
+db3: LEA_DSZ16_ASZ32_SC1
+db8: STAD_DSZ16_ASZ32_SC1
+db9: STADTICKLE_DSZ16_ASZ32_SC1
+dba: LDTICKLE_DSZ16_ASZ32_SC1
+dc0: LDZX_DSZ8_ASZ32_SC4
+dc3: LEA_DSZ8_ASZ32_SC4
+dc8: STAD_DSZ8_ASZ32_SC4
+dc9: STADTICKLE_DSZ8_ASZ32_SC4
+dca: LDTICKLE_DSZ8_ASZ32_SC4
+dcb: PORTIN_DSZ8_ASZ16_SC1
+dcf: PORTOUT_DSZ8_ASZ16_SC1
+dd0: LDZX_DSZ8_ASZ32_SC4
+dd3: LEA_DSZ8_ASZ32_SC4
+dd8: STAD_DSZ8_ASZ32_SC4
+dd9: STADTICKLE_DSZ8_ASZ32_SC4
+dda: LDTICKLE_DSZ8_ASZ32_SC4
+df0: LDZX_DSZ8_ASZ32_SC1
+df3: LEA_DSZ8_ASZ32_SC1
+df8: STAD_DSZ8_ASZ32_SC1
+df9: STADTICKLE_DSZ8_ASZ32_SC1
+dfa: LDTICKLE_DSZ8_ASZ32_SC1
+e00: LDPPHYS_DSZ32_ASZ16_SC1
+e08: STADPPHYS_DSZ32_ASZ16_SC1
+e0a: LDPPHYS_DSZ32_ASZ16_SC1
+e0d: STADPPHYSTICKLE_DSZ32_ASZ16_SC1
+e20: LDPPHYS_DSZ32_ASZ64_SC1
+e25: LDPPHYSTICKLE_DSZ32_ASZ64_SC1
+e28: STADPPHYS_DSZ32_ASZ64_SC1
+e2a: LDPPHYS_DSZ32_ASZ64_SC1
+e2d: STADPPHYSTICKLE_DSZ32_ASZ64_SC1
+e2e: SIMDSTADPPHYS_DSZ32_ASZ64_SC1
+e30: LDPPHYS_DSZ32_ASZ64_SC8
+e38: STADPPHYS_DSZ32_ASZ64_SC8
+e3a: LDPPHYS_DSZ32_ASZ64_SC8
+e40: LDPPHYS_DSZ64_ASZ16_SC1
+e48: STADPPHYS_DSZ64_ASZ16_SC1
+e4a: LDPPHYS_DSZ64_ASZ16_SC1
+e4d: STADPPHYSTICKLE_DSZ64_ASZ16_SC1
+e60: LDPPHYS_DSZ64_ASZ64_SC1
+e65: LDPPHYSTICKLE_DSZ64_ASZ64_SC1
+e68: STADPPHYS_DSZ64_ASZ64_SC1
+e6a: LDPPHYS_DSZ64_ASZ64_SC1
+e6d: STADPPHYSTICKLE_DSZ64_ASZ64_SC1
+e6e: SIMDSTADPPHYS_DSZ64_ASZ64_SC1
+e70: LDPPHYS_DSZ64_ASZ64_SC8
+e75: LDSTGBUF_DSZ64_ASZ16_SC1
+e78: STADPPHYS_DSZ64_ASZ64_SC8
+e7a: LDPPHYS_DSZ64_ASZ64_SC8
+e7d: STADSTGBUF_DSZ64_ASZ16_SC1
+e80: LDPPHYS_DSZ16_ASZ16_SC1
+e88: STADPPHYS_DSZ16_ASZ16_SC1
+e8a: LDPPHYS_DSZ16_ASZ16_SC1
+e8d: STADPPHYSTICKLE_DSZ16_ASZ16_SC1
+ea0: LDPPHYS_DSZ16_ASZ64_SC1
+ea5: LDPPHYSTICKLE_DSZ16_ASZ64_SC1
+ea8: STADPPHYS_DSZ16_ASZ64_SC1
+eaa: LDPPHYS_DSZ16_ASZ64_SC1
+ead: STADPPHYSTICKLE_DSZ16_ASZ64_SC1
+eae: SIMDLSTADSTGBUF_DSZ64_ASZ32_SC1
+eb0: LDPPHYS_DSZ16_ASZ64_SC8
+eb8: STADPPHYS_DSZ16_ASZ64_SC8
+eba: LDPPHYS_DSZ16_ASZ64_SC8
+ec0: LDPPHYS_DSZ8_ASZ16_SC1
+ec8: STADPPHYS_DSZ8_ASZ16_SC1
+eca: LDPPHYS_DSZ8_ASZ16_SC1
+ecb: LDHINT_CACHEALL_ASZ64_SC1
+ecd: STADPPHYSTICKLE_DSZ8_ASZ16_SC1
+edb: LDHINT_CACHE1_ASZ64_SC1
+ee0: LDPPHYS_DSZ8_ASZ64_SC1
+ee5: LDPPHYSTICKLE_DSZ8_ASZ64_SC1
+ee8: STADPPHYS_DSZ8_ASZ64_SC1
+eea: LDPPHYS_DSZ8_ASZ64_SC1
+eeb: LDHINT_CACHE2_ASZ64_SC1
+eed: STADPPHYSTICKLE_DSZ8_ASZ64_SC1
+eee: SIMDHSTADSTGBUF_DSZ64_ASZ32_SC1
+ef0: LDPPHYS_DSZ8_ASZ64_SC8
+ef8: STADPPHYS_DSZ8_ASZ64_SC8
+efa: LDPPHYS_DSZ8_ASZ64_SC8
+f00: LDPPHYS_DSZ32_ASZ32_SC4
+f08: STADPPHYS_DSZ32_ASZ32_SC4
+f0a: LDPPHYS_DSZ32_ASZ32_SC4
+f20: LDPPHYS_DSZ32_ASZ32_SC1
+f28: STADPPHYS_DSZ32_ASZ32_SC1
+f2a: LDPPHYS_DSZ32_ASZ32_SC1
+f30: LDPPHYS_DSZ32_ASZ32_SC8
+f38: STADPPHYS_DSZ32_ASZ32_SC8
+f3a: LDPPHYS_DSZ32_ASZ32_SC8
+f40: LDPPHYS_DSZ64_ASZ32_SC4
+f48: STADPPHYS_DSZ64_ASZ32_SC4
+f4a: LDPPHYS_DSZ64_ASZ32_SC4
+f4b: MPOP
+f4f: MPUSH
+f60: LDPPHYS_DSZ64_ASZ32_SC1
+f65: LDPPHYSTICKLE_DSZ64_ASZ32_SC1
+f68: STADPPHYS_DSZ64_ASZ32_SC1
+f6a: LDPPHYS_DSZ64_ASZ32_SC1
+f6f: MCALL_DIRECT
+f70: LDPPHYS_DSZ64_ASZ32_SC8
+f78: STADPPHYS_DSZ64_ASZ32_SC8
+f7a: LDPPHYS_DSZ64_ASZ32_SC8
+f7f: UCALLPARAM_INDIRECT
+f80: LDPPHYS_DSZ16_ASZ32_SC4
+f88: STADPPHYS_DSZ16_ASZ32_SC4
+f8a: LDPPHYS_DSZ16_ASZ32_SC4
+fa0: LDPPHYS_DSZ16_ASZ32_SC1
+fa8: STADPPHYS_DSZ16_ASZ32_SC1
+faa: LDPPHYS_DSZ16_ASZ32_SC1
+fb0: LDPPHYS_DSZ16_ASZ32_SC8
+fb8: STADPPHYS_DSZ16_ASZ32_SC8
+fba: LDPPHYS_DSZ16_ASZ32_SC8
+fc0: LDPPHYS_DSZ8_ASZ32_SC4
+fc8: STADPPHYS_DSZ8_ASZ32_SC4
+fca: LDPPHYS_DSZ8_ASZ32_SC4
+fe0: LDPPHYS_DSZ8_ASZ32_SC1
+fe8: STADPPHYS_DSZ8_ASZ32_SC1
+fea: LDPPHYS_DSZ8_ASZ32_SC1
+fef: LBSYNC
+ff0: LDPPHYS_DSZ8_ASZ32_SC8
+ff8: STADPPHYS_DSZ8_ASZ32_SC8
+ffa: LDPPHYS_DSZ8_ASZ32_SC8
+fff: SFENCE