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Add Maxim external LED drivers, MAX7219 or MAX7951, for front panel lamps
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125
Testbench_panel_LEDs.vhd
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125
Testbench_panel_LEDs.vhd
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@ -0,0 +1,125 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:16:46 06/18/2015
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-- Design Name:
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-- Module Name: C:/Users/lwilkinson/Documents/Xilinx/IBM2030/Testbench_panel_LEDs.vhd
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-- Project Name: IBM2030
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: panel_LEDs
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Testbench_panel_LEDs IS
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END Testbench_panel_LEDs;
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ARCHITECTURE behavior OF Testbench_panel_LEDs IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT panel_LEDs
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PORT(
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LEDs : IN std_logic_vector(0 to 255);
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clk : IN std_logic;
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MAX7219_CLK : OUT std_logic;
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MAX7219_DIN0 : OUT std_logic;
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MAX7219_DIN1 : OUT std_logic;
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MAX7219_DIN2 : OUT std_logic;
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MAX7219_DIN3 : OUT std_logic;
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MAX7219_LOAD : OUT std_logic;
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MAX6951_CLK : OUT std_logic;
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MAX6951_DIN : OUT std_logic;
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MAX6951_CS0 : OUT std_logic;
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MAX6951_CS1 : OUT std_logic;
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MAX6951_CS2 : OUT std_logic;
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MAX6951_CS3 : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal LEDs : std_logic_vector(0 to 255) := (1 => '1',3 => '1',5 => '1',7 => '1',9 => '1',11 => '1',13 => '1',15 => '1',17 => '1',others => '0');
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signal clk : std_logic := '0';
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--Outputs
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signal MAX7219_CLK : std_logic;
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signal MAX7219_DIN0 : std_logic;
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signal MAX7219_DIN1 : std_logic;
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signal MAX7219_DIN2 : std_logic;
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signal MAX7219_DIN3 : std_logic;
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signal MAX7219_LOAD : std_logic;
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signal MAX6951_CLK : std_logic;
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signal MAX6951_DIN : std_logic;
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signal MAX6951_CS0 : std_logic;
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signal MAX6951_CS1 : std_logic;
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signal MAX6951_CS2 : std_logic;
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signal MAX6951_CS3 : std_logic;
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-- Clock period definitions
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constant clk_period : time := 20 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: panel_LEDs PORT MAP (
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LEDs => LEDs,
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clk => clk,
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MAX7219_CLK => MAX7219_CLK,
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MAX7219_DIN0 => MAX7219_DIN0,
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MAX7219_DIN1 => MAX7219_DIN1,
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MAX7219_DIN2 => MAX7219_DIN2,
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MAX7219_DIN3 => MAX7219_DIN3,
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MAX7219_LOAD => MAX7219_LOAD,
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MAX6951_CLK => MAX6951_CLK,
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MAX6951_DIN => MAX6951_DIN,
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MAX6951_CS0 => MAX6951_CS0,
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MAX6951_CS1 => MAX6951_CS1,
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MAX6951_CS2 => MAX6951_CS2,
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MAX6951_CS3 => MAX6951_CS3
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for 1ms;
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-- insert stimulus here
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wait;
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end process;
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END;
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@ -155,7 +155,7 @@ constant indLayout : screenIndicators :=
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-- To convert ASCII to the internal 6-bit representation...
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-- Not all characters are needed, so some special ones are added
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subtype characterCode is std_logic_vector(6 downto 0);
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type charArray is array(character'(' ') to character'('{')) of characterCode;
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type charArray is array(32 to 123) of characterCode;
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constant charTranslate : charArray := (
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-- 20->62, 21 ! ->61, 22-23->127, 24->59, 25-29->127, 2A->60, 2B-2F->127
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"0111110","0111101","1111111","1111111","0111011","1111111","1111111","1111111",
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@ -1527,7 +1527,7 @@ function initScreen (constant screen : screenType) return screenCharacters is
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begin
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for r in lines loop
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for c in columns loop
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sc(r,c) := charTranslate(screen(r,c));
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sc(r,c) := charTranslate(character'pos(screen(r,c)));
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end loop;
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end loop;
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return sc;
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215
ibm2030.vhd
215
ibm2030.vhd
@ -174,6 +174,9 @@ signal N60_CY_TIMER_PULSE : STD_LOGIC; -- Used for the Interval Timer
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signal Clock1ms : STD_LOGIC; -- 1kHz clock for single-shots etc.
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signal DEBUG : DEBUG_BUS; -- Passed to all modeles to probe signals
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signal LED_vector : std_logic_vector(0 to 255);
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begin
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cpu : entity cpu port map (
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@ -479,7 +482,7 @@ begin
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-- Clocks etc.
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clk => clk, -- 50MHz clock
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Clock1ms => Clock1ms,
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-- Clock1ms => Clock1ms,
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Timer => N60_CY_TIMER_PULSE -- Output from Switches is actually 50Hz
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);
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@ -503,7 +506,217 @@ begin
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clk => clk
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);
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sramaddr(17) <= '0';
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LED_vector <= (
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0 => IND_SALS.SALS_PA,
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1 => IND_SALS.SALS_CN(5),
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2 => IND_SALS.SALS_CN(4),
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3 => IND_SALS.SALS_CN(3),
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4 => IND_SALS.SALS_CN(2),
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5 => IND_SALS.SALS_CN(1),
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6 => IND_SALS.SALS_CN(0),
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7 => IND_SALS.SALS_PN,
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8 => X_IND_P,
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9 => WX_IND(4),
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10 => WX_IND(3),
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11 => WX_IND(2),
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12 => WX_IND(1),
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13 => WX_IND(0),
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14 => W_IND_P,
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15 => '0', -- LP
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16 => WX_IND(12),
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17 => WX_IND(11),
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18 => WX_IND(10),
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19 => WX_IND(9),
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20 => WX_IND(8),
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21 => WX_IND(7),
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22 => WX_IND(6),
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23 => WX_IND(5),
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24 => IND_SALS.SALS_CL(2),
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25 => IND_SALS.SALS_CL(1),
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26 => IND_SALS.SALS_CL(0),
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27 => IND_SALS.SALS_CH(3),
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28 => IND_SALS.SALS_CH(2),
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29 => IND_SALS.SALS_CH(1),
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30 => IND_SALS.SALS_CH(0),
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31 => IND_SALS.SALS_PA,
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32 => IND_SALS.SALS_CB(1),
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33 => IND_SALS.SALS_CB(0),
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34 => IND_SALS.SALS_CA(3),
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35 => IND_SALS.SALS_CA(2),
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36 => IND_SALS.SALS_CA(1),
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37 => IND_SALS.SALS_CA(0),
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38 => IND_SALS.SALS_AA,
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39 => IND_SALS.SALS_CL(3),
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40 => IND_SALS.SALS_CK(0),
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41 => IND_SALS.SALS_PK,
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42 => IND_SALS.SALS_AK,
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43 => IND_SALS.SALS_CU(1),
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44 => IND_SALS.SALS_CU(0),
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45 => IND_SALS.SALS_CM(2),
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46 => IND_SALS.SALS_CM(1),
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47 => IND_SALS.SALS_CM(0),
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48 => IND_SALS.SALS_CD(3),
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49 => IND_SALS.SALS_CD(2),
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50 => IND_SALS.SALS_CD(1),
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51 => IND_SALS.SALS_CD(0),
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52 => IND_SALS.SALS_PC,
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53 => IND_SALS.SALS_CK(3),
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54 => IND_SALS.SALS_CK(2),
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55 => IND_SALS.SALS_CK(1),
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56 => IND_SALS.SALS_CC(0),
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57 => IND_SALS.SALS_CV(1),
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58 => IND_SALS.SALS_CV(0),
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59 => IND_SALS.SALS_CG(1),
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60 => IND_SALS.SALS_CG(0),
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61 => IND_SALS.SALS_CF(2),
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62 => IND_SALS.SALS_CF(1),
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63 => IND_SALS.SALS_CF(0),
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-- Count
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-- SX1
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-- SX2
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160 => IND_ADDR_IN,
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161 => IND_OPNL_IN,
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168 => IND_FO_P,
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169 => IND_SUPPR_OUT,
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170 => IND_SERV_OUT,
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171 => IND_CMMD_OUT,
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172 => IND_ADDR_OUT,
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173 => IND_SEL_OUT,
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174 => IND_SERV_IN,
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175 => IND_STATUS_IN,
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176 => IND_FO(7),
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177 => IND_FO(6),
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178 => IND_FO(5),
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179 => IND_FO(4),
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180 => IND_FO(3),
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181 => IND_FO(2),
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182 => IND_FO(1),
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183 => IND_FO(0),
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184 => IND_M(6),
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185 => IND_M(5),
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186 => IND_M(4),
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187 => IND_M(3),
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188 => IND_M(2),
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189 => IND_M(1),
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190 => IND_M(0),
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191 => IND_M(8),
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192 => IND_N(5),
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193 => IND_N(4),
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194 => IND_N(3),
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195 => IND_N(2),
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196 => IND_N(1),
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197 => IND_N(0),
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198 => IND_N(8),
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199 => IND_M(7),
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200 => IND_MSDR(2),
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201 => IND_MSDR(1),
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202 => IND_MSDR(0),
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203 => IND_MSDR_P,
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204 => IND_LOC_STG,
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205 => IND_MAIN_STG,
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206 => IND_N(7),
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207 => IND_N(6),
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208 => IND_ALU(1),
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209 => IND_ALU(0),
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210 => IND_ALU(8),
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211 => IND_MSDR(7),
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212 => IND_MSDR(6),
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213 => IND_MSDR(5),
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214 => IND_MSDR(4),
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215 => IND_MSDR(3),
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216 => IND_B(0),
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217 => IND_B(8),
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218 => IND_ALU(7),
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219 => IND_ALU(6),
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220 => IND_ALU(5),
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221 => IND_ALU(4),
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222 => IND_ALU(3),
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223 => IND_ALU(2),
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224 => IND_A(8),
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225 => IND_B(7),
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226 => IND_B(6),
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227 => IND_B(5),
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228 => IND_B(4),
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229 => IND_B(3),
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230 => IND_B(2),
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231 => IND_B(1),
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232 => IND_A(7),
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233 => IND_A(6),
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234 => IND_A(5),
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235 => IND_A(4),
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236 => IND_A(3),
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237 => IND_A(2),
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238 => IND_A(1),
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239 => IND_A(0),
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240 => IND_CHK_B_REG,
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241 => IND_1050_REQ,
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242 => IND_1050_INTRV,
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243 => IND_CHK_STOR_DATA,
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244 => IND_CHK_STOR_ADDR,
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245 => IND_ALLOW_WR,
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246 => IND_CY_MATCH,
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247 => IND_EX,
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248 => IND_CHK_CTRL_REG,
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249 => IND_CHK_ROS_SALS,
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250 => IND_CHK_ROS_ADDR,
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251 => IND_COMP_MODE,
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252 => IND_SEL_CHNL,
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253 => IND_MPX,
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254 => IND_CHK_ALU,
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255 => IND_CHK_A_REG,
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others => '0');
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front_panel : entity panel_LEDs
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generic map(
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clock_divider => 2,
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number_LEDs => 256
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)
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port map(
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clk => clk,
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LEDs => LED_vector,
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-- (
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-- 0 => W_IND_P,
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-- 0 => IND_SALS.SALS_PA,
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-- 1 => IND_SALS.SALS_CN(5),
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-- 2 => IND_SALS.SALS_CN(4),
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-- 3 => IND_SALS.SALS_CN(3),
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-- 4 => IND_SALS.SALS_CN(2),
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-- 5 => IND_SALS.SALS_CN(1),
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-- 6 => IND_SALS.SALS_CN(0),
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-- 7 => IND_SALS.SALS_PN,
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-- 16#01# to 16#0F# => '0',
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-- 16#10# to 16#1F# => '0',
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-- 16#20# to 16#2F# => '0',
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-- 16#30# to 16#3F# => '0',
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-- 16#40# to 16#4F# => '0',
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-- 16#50# to 16#5F# => '0',
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-- 16#60# to 16#6F# => '0',
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-- 16#70# to 16#7F# => '0',
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-- 16#80# to 16#8F# => '0',
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-- 16#90# to 16#9F# => '0',
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-- 16#A0# to 16#AF# => '0',
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-- 16#B0# to 16#BF# => '0',
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-- 16#C0# to 16#CF# => '0',
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-- 16#D0# to 16#DF# => '0',
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-- 16#E0# to 16#EF# => '0',
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-- 16#F0# to 16#FF# => '0'
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-- ),
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-- MAX7219 is standard LED mux (full-size panel)
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MAX7219_CLK => open,
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MAX7219_LOAD => open,
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MAX7219_DIN0 => open,
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MAX7219_DIN1 => open,
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MAX7219_DIN2 => open,
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MAX7219_DIN3 => open,
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-- MAX6951 is charlieplexed LED mux (miniature panel)
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MAX6951_CLK => open,
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MAX6951_CS0 => open,
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MAX6951_CS1 => open,
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MAX6951_CS2 => open,
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MAX6951_CS3 => open,
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MAX6951_DIN => open
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);
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DEBUG.Selection <= CONV_INTEGER(unsigned(SW_J));
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360
panel_LEDs.vhd
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360
panel_LEDs.vhd
Normal file
@ -0,0 +1,360 @@
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---------------------------------------------------------------------------
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-- Copyright © 2015 Lawrence Wilkinson lawrence@ljw.me.uk
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--
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-- This file is part of LJW2030, a VHDL implementation of the IBM
|
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-- System/360 Model 30.
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--
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-- LJW2030 is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
|
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-- the Free Software Foundation, either version 3 of the License, or
|
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-- (at your option) any later version.
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--
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-- LJW2030 is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
|
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-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
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--
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---------------------------------------------------------------------------
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--
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-- File: panel_LEDs.vhd
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-- Creation Date: 16:08:00 16/06/2015
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-- Description:
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-- 360/30 Front Panel LED lamp drivers
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-- This drives 256 front panel LEDs via Maxim SPI/I2C multiplexed drivers
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-- There are two options:
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-- MAX7219 8 x 8 multiplexed LEDs
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-- MAX7951 Charlieplexed LEDs
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-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
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-- for the 360/30 R25-5103-1
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-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
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-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
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-- Gate A is the main logic gate, B is the second (optional) logic gate,
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-- C is the core storage and X is the CCROS unit
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--
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-- Revision History:
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-- Revision 1.0 2010-07-09
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-- Initial Release
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.Buses_package.all;
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use work.Gates_package.EvenParity;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity panel_LEDs is
|
||||
Generic (
|
||||
Clock_divider : integer := 2; -- Default for 50MHz clock is 25MHz = 40ns = 20ns + 20ns
|
||||
Number_LEDs : integer := 256
|
||||
);
|
||||
Port ( -- Lamp input vector
|
||||
LEDs : in std_logic_vector(0 to Number_LEDs-1);
|
||||
-- Other inputs
|
||||
clk : in STD_LOGIC; -- 50MHz
|
||||
|
||||
-- Driver outputs
|
||||
MAX7219_CLK : out std_logic;
|
||||
MAX7219_DIN0 : out std_logic; -- LEDs 00-3F
|
||||
MAX7219_DIN1 : out std_logic; -- LEDs 40-7F
|
||||
MAX7219_DIN2 : out std_logic; -- LEDs 80-BF
|
||||
MAX7219_DIN3 : out std_logic; -- LEDs C0-FF
|
||||
MAX7219_LOAD : out std_logic; -- Data latched on rising edge
|
||||
|
||||
MAX6951_CLK : out std_logic;
|
||||
MAX6951_DIN : out std_logic; --
|
||||
MAX6951_CS0 : out std_logic; -- LEDs 00-3F Data latched on rising edge
|
||||
MAX6951_CS1 : out std_logic; -- LEDs 40-7F Data latched on rising edge
|
||||
MAX6951_CS2 : out std_logic; -- LEDs 80-BF Data latched on rising edge
|
||||
MAX6951_CS3 : out std_logic -- LEDs C0-FF Data latched on rising edge
|
||||
);
|
||||
end panel_LEDs;
|
||||
|
||||
architecture Behavioral of panel_LEDs is
|
||||
signal clk_out : std_logic := '0';
|
||||
|
||||
-- MAX7219 data is 8b address and 8b data
|
||||
-- Address is:
|
||||
-- 00 No-op (unused)
|
||||
-- 01 Digit 0 (in position 0)
|
||||
-- ...
|
||||
-- 08 Digit 7 (in position 0)
|
||||
-- 09 Decode mode (fixed at default)
|
||||
-- 0A Intensity (fixed at 0F in position 8)
|
||||
-- 0B Scan limit (fixed at 07 in position 9)
|
||||
-- 0C Shutdown (fixed at 01 in position 10)
|
||||
-- 0F Display test (fixed at 00 in position 11)
|
||||
|
||||
type registers7219 is array(0 to 3,0 to 11) of std_logic_vector(15 downto 0);
|
||||
signal max7219_vector : registers7219 :=
|
||||
(
|
||||
0 => (
|
||||
0 => "0000000000000000",
|
||||
1 => "0000000100000000",
|
||||
2 => "0000001000000000",
|
||||
3 => "0000001100000000",
|
||||
4 => "0000010000000000",
|
||||
5 => "0000010100000000",
|
||||
6 => "0000011000000000",
|
||||
7 => "0000011100000000",
|
||||
8 => "0000101000000000",
|
||||
9 => "0000101100000111",
|
||||
10 => "0000110000000001",
|
||||
11 => "0000111100000000"
|
||||
|
||||
),
|
||||
1 => (
|
||||
0 => "0000000000000000",
|
||||
1 => "0000000100000000",
|
||||
2 => "0000001000000000",
|
||||
3 => "0000001100000000",
|
||||
4 => "0000010000000000",
|
||||
5 => "0000010100000000",
|
||||
6 => "0000011000000000",
|
||||
7 => "0000011100000000",
|
||||
8 => "0000101000000000",
|
||||
9 => "0000101100000111",
|
||||
10 => "0000110000000001",
|
||||
11 => "0000111100000000"
|
||||
),
|
||||
2 => (
|
||||
0 => "0000000000000000",
|
||||
1 => "0000000100000000",
|
||||
2 => "0000001000000000",
|
||||
3 => "0000001100000000",
|
||||
4 => "0000010000000000",
|
||||
5 => "0000010100000000",
|
||||
6 => "0000011000000000",
|
||||
7 => "0000011100000000",
|
||||
8 => "0000101000000000",
|
||||
9 => "0000101100000111",
|
||||
10 => "0000110000000001",
|
||||
11 => "0000111100000000"
|
||||
),
|
||||
3 => (
|
||||
0 => "0000000000000000",
|
||||
1 => "0000000100000000",
|
||||
2 => "0000001000000000",
|
||||
3 => "0000001100000000",
|
||||
4 => "0000010000000000",
|
||||
5 => "0000010100000000",
|
||||
6 => "0000011000000000",
|
||||
7 => "0000011100000000",
|
||||
8 => "0000101000000000",
|
||||
9 => "0000101100000111",
|
||||
10 => "0000110000000001",
|
||||
11 => "0000111100000000"
|
||||
)
|
||||
);
|
||||
|
||||
|
||||
-- MAX6951 data is 8b Address and 8b Data
|
||||
-- Address is:
|
||||
-- 00 No-op (unused)
|
||||
-- 01 Decode mode (fixed at default)
|
||||
-- 02 Intensity (fixed at 0F in position 8)
|
||||
-- 03 Scan limit (fixed at 07 in position 9)
|
||||
-- 04 Configuration (fixed at 01 in position 10)
|
||||
-- 07 Display test (fixed at 00 in position 11)
|
||||
-- 60 Digit 0 (in position 0)
|
||||
-- ...
|
||||
-- 67 Digit 7 (in position 0)
|
||||
type registers6951 is array(0 to 3,0 to 11) of std_logic_vector(15 downto 0);
|
||||
signal max6951_vector : registers6951 :=
|
||||
(
|
||||
0 => (
|
||||
0 => "0110000000000000",
|
||||
1 => "0110000100000000",
|
||||
2 => "0110001000000000",
|
||||
3 => "0110001100000000",
|
||||
4 => "0110010000000000",
|
||||
5 => "0110010100000000",
|
||||
6 => "0110011000000000",
|
||||
7 => "0110011100000000",
|
||||
8 => "0000001000000000",
|
||||
9 => "0000001100000111",
|
||||
10 => "0000010000000001",
|
||||
11 => "0000011100000000"
|
||||
|
||||
),
|
||||
1 => (
|
||||
0 => "0110000000000000",
|
||||
1 => "0110000100000000",
|
||||
2 => "0110001000000000",
|
||||
3 => "0110001100000000",
|
||||
4 => "0110010000000000",
|
||||
5 => "0110010100000000",
|
||||
6 => "0110011000000000",
|
||||
7 => "0110011100000000",
|
||||
8 => "0000001000000000",
|
||||
9 => "0000001100000111",
|
||||
10 => "0000010000000001",
|
||||
11 => "0000011100000000"
|
||||
),
|
||||
2 => (
|
||||
0 => "0110000000000000",
|
||||
1 => "0110000100000000",
|
||||
2 => "0110001000000000",
|
||||
3 => "0110001100000000",
|
||||
4 => "0110010000000000",
|
||||
5 => "0110010100000000",
|
||||
6 => "0110011000000000",
|
||||
7 => "0110011100000000",
|
||||
8 => "0000001000000000",
|
||||
9 => "0000001100000111",
|
||||
10 => "0000010000000001",
|
||||
11 => "0000011100000000"
|
||||
),
|
||||
3 => (
|
||||
0 => "0110000000000000",
|
||||
1 => "0110000100000000",
|
||||
2 => "0110001000000000",
|
||||
3 => "0110001100000000",
|
||||
4 => "0110010000000000",
|
||||
5 => "0110010100000000",
|
||||
6 => "0110011000000000",
|
||||
7 => "0110011100000000",
|
||||
8 => "0000001000000000",
|
||||
9 => "0000001100000111",
|
||||
10 => "0000010000000001",
|
||||
11 => "0000011100000000"
|
||||
)
|
||||
);
|
||||
begin
|
||||
gen_clk : process (clk) is
|
||||
variable divider : integer := Clock_divider;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if (divider=0) then
|
||||
divider := Clock_divider;
|
||||
clk_out <= not clk_out;
|
||||
MAX7219_CLK <= not clk_out;
|
||||
MAX6951_CLK <= not clk_out;
|
||||
else
|
||||
divider := divider - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
max7219 : process (clk_out) is
|
||||
variable reg_counter : integer := 0;
|
||||
variable bit_counter : integer := 16;
|
||||
variable shift_reg0,shift_reg1,shift_reg2,shift_reg3 : std_logic_vector(16 downto 0);
|
||||
begin
|
||||
if falling_edge(clk_out) then
|
||||
if bit_counter=0 then
|
||||
bit_counter := 16;
|
||||
if reg_counter=9 then
|
||||
reg_counter := 0;
|
||||
else
|
||||
if reg_counter=9 then
|
||||
reg_counter := 0;
|
||||
else
|
||||
reg_counter := reg_counter + 1;
|
||||
end if;
|
||||
case reg_counter is
|
||||
when 0 to 7 =>
|
||||
shift_reg0 := '0' & max7219_vector(0,reg_counter)(15 downto 8) & LEDs(reg_counter*8+0 to reg_counter*8+7);
|
||||
shift_reg1 := '0' & max7219_vector(1,reg_counter)(15 downto 8) & LEDs(reg_counter*8+64 to reg_counter*8+71);
|
||||
shift_reg2 := '0' & max7219_vector(2,reg_counter)(15 downto 8) & LEDs(reg_counter*8+128 to reg_counter*8+135);
|
||||
shift_reg3 := '0' & max7219_vector(3,reg_counter)(15 downto 8) & LEDs(reg_counter*8+192 to reg_counter*8+199);
|
||||
when others =>
|
||||
shift_reg0 := '0' & max7219_vector(0,reg_counter);
|
||||
shift_reg1 := '0' & max7219_vector(1,reg_counter);
|
||||
shift_reg2 := '0' & max7219_vector(2,reg_counter);
|
||||
shift_reg3 := '0' & max7219_vector(3,reg_counter);
|
||||
end case;
|
||||
end if;
|
||||
else
|
||||
bit_counter := bit_counter - 1;
|
||||
shift_reg0 := shift_reg0(15 downto 0) & '0';
|
||||
shift_reg1 := shift_reg1(15 downto 0) & '0';
|
||||
shift_reg2 := shift_reg2(15 downto 0) & '0';
|
||||
shift_reg3 := shift_reg3(15 downto 0) & '0';
|
||||
end if;
|
||||
if bit_counter=16 then
|
||||
MAX7219_LOAD <= '1';
|
||||
else
|
||||
MAX7219_LOAD <= '0';
|
||||
end if;
|
||||
MAX7219_DIN0 <= shift_reg0(16);
|
||||
MAX7219_DIN1 <= shift_reg1(16);
|
||||
MAX7219_DIN2 <= shift_reg2(16);
|
||||
MAX7219_DIN3 <= shift_reg3(16);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
max6951 : process (clk_out) is
|
||||
variable dev_counter : integer := 3;
|
||||
variable reg_counter : integer := 0;
|
||||
variable bit_counter : integer := 16;
|
||||
variable shift_reg : std_logic_vector(16 downto 0);
|
||||
begin
|
||||
if falling_edge(clk_out) then
|
||||
if bit_counter=0 then
|
||||
bit_counter := 16;
|
||||
if reg_counter=9 then
|
||||
if dev_counter=0 then
|
||||
dev_counter := 3;
|
||||
else
|
||||
dev_counter := dev_counter - 1;
|
||||
end if;
|
||||
reg_counter := 0;
|
||||
else
|
||||
if reg_counter=9 then
|
||||
reg_counter := 0;
|
||||
else
|
||||
reg_counter := reg_counter + 1;
|
||||
end if;
|
||||
case reg_counter is
|
||||
when 0 to 7 =>
|
||||
shift_reg := '0' & max6951_vector(dev_counter,reg_counter)(15 downto 8) & LEDs(dev_counter*64+reg_counter*8 to dev_counter*64+reg_counter*8+7);
|
||||
when others =>
|
||||
shift_reg := '0' & max6951_vector(dev_counter,reg_counter);
|
||||
end case;
|
||||
end if;
|
||||
else
|
||||
bit_counter := bit_counter - 1;
|
||||
shift_reg := shift_reg(15 downto 0) & '0';
|
||||
end if;
|
||||
if bit_counter=16 then
|
||||
MAX6951_CS0 <= '1';
|
||||
MAX6951_CS1 <= '1';
|
||||
MAX6951_CS2 <= '1';
|
||||
MAX6951_CS3 <= '1';
|
||||
else
|
||||
if dev_counter=0 then
|
||||
MAX6951_CS0 <= '0';
|
||||
else
|
||||
MAX6951_CS0 <= '1';
|
||||
end if;
|
||||
if dev_counter=1 then
|
||||
MAX6951_CS1 <= '0';
|
||||
else
|
||||
MAX6951_CS1 <= '1';
|
||||
end if;
|
||||
if dev_counter=2 then
|
||||
MAX6951_CS2 <= '0';
|
||||
else
|
||||
MAX6951_CS2 <= '1';
|
||||
end if;
|
||||
if dev_counter=3 then
|
||||
MAX6951_CS3 <= '0';
|
||||
else
|
||||
MAX6951_CS3 <= '1';
|
||||
end if;
|
||||
end if;
|
||||
MAX6951_DIN <= shift_reg(16);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavioral;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user