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https://github.com/ibm2030/IBM2030.git
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126 lines
3.5 KiB
VHDL
126 lines
3.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:16:46 06/18/2015
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-- Design Name:
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-- Module Name: C:/Users/lwilkinson/Documents/Xilinx/IBM2030/Testbench_panel_LEDs.vhd
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-- Project Name: IBM2030
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: panel_LEDs
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Testbench_panel_LEDs IS
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END Testbench_panel_LEDs;
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ARCHITECTURE behavior OF Testbench_panel_LEDs IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT panel_LEDs
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PORT(
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LEDs : IN std_logic_vector(0 to 255);
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clk : IN std_logic;
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MAX7219_CLK : OUT std_logic;
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MAX7219_DIN0 : OUT std_logic;
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MAX7219_DIN1 : OUT std_logic;
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MAX7219_DIN2 : OUT std_logic;
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MAX7219_DIN3 : OUT std_logic;
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MAX7219_LOAD : OUT std_logic;
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MAX6951_CLK : OUT std_logic;
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MAX6951_DIN : OUT std_logic;
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MAX6951_CS0 : OUT std_logic;
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MAX6951_CS1 : OUT std_logic;
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MAX6951_CS2 : OUT std_logic;
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MAX6951_CS3 : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal LEDs : std_logic_vector(0 to 255) := (1 => '1',3 => '1',5 => '1',7 => '1',9 => '1',11 => '1',13 => '1',15 => '1',17 => '1',others => '0');
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signal clk : std_logic := '0';
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--Outputs
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signal MAX7219_CLK : std_logic;
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signal MAX7219_DIN0 : std_logic;
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signal MAX7219_DIN1 : std_logic;
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signal MAX7219_DIN2 : std_logic;
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signal MAX7219_DIN3 : std_logic;
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signal MAX7219_LOAD : std_logic;
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signal MAX6951_CLK : std_logic;
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signal MAX6951_DIN : std_logic;
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signal MAX6951_CS0 : std_logic;
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signal MAX6951_CS1 : std_logic;
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signal MAX6951_CS2 : std_logic;
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signal MAX6951_CS3 : std_logic;
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-- Clock period definitions
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constant clk_period : time := 20 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: panel_LEDs PORT MAP (
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LEDs => LEDs,
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clk => clk,
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MAX7219_CLK => MAX7219_CLK,
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MAX7219_DIN0 => MAX7219_DIN0,
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MAX7219_DIN1 => MAX7219_DIN1,
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MAX7219_DIN2 => MAX7219_DIN2,
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MAX7219_DIN3 => MAX7219_DIN3,
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MAX7219_LOAD => MAX7219_LOAD,
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MAX6951_CLK => MAX6951_CLK,
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MAX6951_DIN => MAX6951_DIN,
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MAX6951_CS0 => MAX6951_CS0,
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MAX6951_CS1 => MAX6951_CS1,
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MAX6951_CS2 => MAX6951_CS2,
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MAX6951_CS3 => MAX6951_CS3
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for 1ms;
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-- insert stimulus here
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wait;
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end process;
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END;
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