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This commit is contained in:
Lawrence Wilkinson 2013-04-16 22:44:40 +01:00
parent e41592aa5f
commit cd21e989a7
39 changed files with 9452 additions and 543 deletions
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106
Buses2030.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -27,8 +27,8 @@
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Add Storage and 1050 interfaces
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -133,8 +133,106 @@ type MPX_TAGS_IN is record
REQ_IN,
MTR_IN : STD_LOGIC;
end record MPX_TAGS_IN;
-- List of front panel indicators
subtype IndicatorRange is integer range 0 to 249; -- 218 through 249 are temp debug items
type STORAGE_IN_INTERFACE is record
ReadData : std_logic_vector(0 to 8);
end record STORAGE_IN_INTERFACE;
type STORAGE_OUT_INTERFACE is record
MSAR : std_logic_vector(0 to 15);
MainStorage : std_logic;
WritePulse : std_logic;
ReadPulse : std_logic;
WriteData : std_logic_vector(0 to 8);
end record STORAGE_OUT_INTERFACE;
-- CE connections on 1050 interface
type CE_IN is record
CE_BIT : STD_LOGIC_VECTOR(0 to 7);
CE_MODE : STD_LOGIC;
CE_TI_OR_TE_RUN_MODE : STD_LOGIC;
CE_SEL_OUT : STD_LOGIC;
CE_EXIT_MPLX_SHARE : STD_LOGIC;
CE_DATA_ENTER_NO : STD_LOGIC;
CE_DATA_ENTER_NC : STD_LOGIC;
CE_TI_DECODE : STD_LOGIC;
CE_TE_DECODE : STD_LOGIC;
CE_TA_DECODE : STD_LOGIC;
CE_RESET : STD_LOGIC;
end record CE_IN ;
type CE_OUT is record
PTT_BITS : STD_LOGIC_VECTOR(0 to 6);
DATA_REG : STD_LOGIC_VECTOR(0 to 7);
RDR_1_CLUTCH : STD_LOGIC;
WRITE_UC : STD_LOGIC;
XLATE_UC : STD_LOGIC;
PUNCH_1_CLUTCH : STD_LOGIC;
NPL : STD_LOGIC_VECTOR(0 to 7);
OUTPUT_SEL_AND_RDY : STD_LOGIC;
TT : STD_LOGIC_VECTOR(0 to 7);
CPU_REQUEST_IN : STD_LOGIC;
n1050_OP_IN : STD_LOGIC;
HOME_RDR_STT_LCH : STD_LOGIC;
RDR_ON_LCH : STD_LOGIC;
MICRO_SHARE_LCH : STD_LOGIC;
PROCEED_LCH : STD_LOGIC;
TA_REG_POS_4 : STD_LOGIC;
CR_LF : STD_LOGIC;
TA_REG_POS_6 : STD_LOGIC;
n1050_RST : STD_LOGIC;
end record CE_OUT;
type PCH_CONN is record -- serialIn @ 1050 -> CPU signals
-- Input device (keyboard) input connections:
PCH_BITS : STD_LOGIC_VECTOR(0 to 6);
PCH_1_CLUTCH_1050 : STD_LOGIC;
-- Output device (printer) input connections:
RDR_2_READY : STD_LOGIC;
HOME_RDR_STT_LCH : STD_LOGIC;
HOME_OUTPUT_DEV_RDY : STD_LOGIC;
RDR_1_CLUTCH_1050 : STD_LOGIC;
-- Other inputs
CPU_CONNECTED : STD_LOGIC;
REQ_KEY : STD_LOGIC;
end record PCH_CONN;
type RDR_CONN is record -- serialOut : CPU -> 1050 signals
-- Output device (printer) output connections:
RDR_BITS : STD_LOGIC_VECTOR(0 to 6);
RD_STROBE : STD_LOGIC;
end record RDR_CONN;
type CONN_1050 is record -- serialControl : CPU -> 1050 signals
n1050_RST_LCH,
n1050_RESET,
HOME_RDR_START,
PROCEED,
RDR_2_HOLD,
CARR_RETURN_AND_LINE_FEED,
RESTORE : STD_LOGIC;
end record CONN_1050;
type Serial_Output_Lines is record
SerialTx : STD_LOGIC; -- Printer data
RTS : STD_LOGIC; -- Request to send - Keyboard ok to send
DTR : STD_LOGIC; -- Data terminal ready - Printer activated
end record Serial_Output_Lines;
type Serial_Input_Lines is record
SerialRx : STD_LOGIC;
DCD : STD_LOGIC; -- Carrier Detect - Keyboard ready
DSR : STD_LOGIC; -- Data Set Ready - 1050 Ready
RI : STD_LOGIC; -- Ring Indicator - Unused
CTS : STD_LOGIC; -- Clear to send - Printer ready to accept data
end record Serial_Input_Lines;
type DEBUG_BUS is record
Selection : integer range 0 to 15;
Probe : STD_LOGIC;
end record DEBUG_BUS;
end package Buses_package;

58
FMD2030_5-01A-B.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,9 @@
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Changes to PA check latch
-- Use T1 rather than P1 to latch WX
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -61,7 +62,7 @@ port (
SALS : IN SALS_Bus; -- 01C
-- Clock inputs
T2,T3,T4 : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
clk : IN STD_LOGIC;
@ -116,7 +117,7 @@ port (
TEST_LAMP : IN STD_LOGIC; -- ?????
-- Debug
DEBUG : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Outputs
SET_IND_ROSAR : OUT STD_LOGIC; --- 01AB2 to 07AB3
@ -143,7 +144,8 @@ signal sSET_IND_ROSAR : STD_LOGIC;
signal sWX : STD_LOGIC_VECTOR(0 to 12);
signal sINH_NORM_ENTRY : STD_LOGIC;
signal sCTRL_REG_CHK : STD_LOGIC;
signal sSAL_PC : STD_LOGIC;
signal sSAL_PC : STD_LOGIC;
signal PA_LCH : STD_LOGIC;
-- WX display
signal WX_IND_X : STD_LOGIC_VECTOR(0 to 12);
signal W_IND_P_X, X_IND_P_X : STD_LOGIC;
@ -172,10 +174,9 @@ BEGIN
-- ROS Indicator register
ROSAR_IND_LATCH_Set <= (ANY_MACH_CHK and CHK_OR_DIAG_STOP_SW) or EARLY_ROAR_STOP;
ROSAR_IND_LATCH: FLL port map(ROSAR_IND_LATCH_Set,MACH_START_RST,FL_ROSAR_IND); -- AA3G4,AA3H4
-- sSET_IND_ROSAR <= (not ALU_CHK or not CHK_OR_DIAG_STOP_SW) and not FL_ROSAR_IND; -- AA3H4
sSET_IND_ROSAR <= '1'; -- Debug
sSET_IND_ROSAR <= (not ALU_CHK or not CHK_OR_DIAG_STOP_SW) and not FL_ROSAR_IND; -- AA3H4
-- sSET_IND_ROSAR <= '1'; -- Debug
SET_IND_ROSAR <= sSET_IND_ROSAR;
DEBUG <= FL_ROSAR_IND;
SET_IND <= (T4 and sSET_IND_ROSAR) or MACH_RST_SET_LCH; -- AA3J4
WINDP: PH port map(W_P,SET_IND,W_IND_P_X); -- AA3J2
@ -185,9 +186,12 @@ X_IND_P <= X_IND_P_X or TEST_LAMP;
WXIND: PHV13 port map(sWX,SET_IND,WX_IND_X); -- AA3J2,AA3J3
WX_IND <= WX_IND_X or (WX_IND'range=>TEST_LAMP);
-- SALS parity checking
WX_CHK <= not(SALS.SALS_PA xor W_IND_P_X xor X_IND_P_X); -- AA2J4 ?? Inverted ??
-- WX_CHK <= not(SALS.SALS_PA xor W_P xor X_P); -- AA2J4 ?? or W_IND_P_X, X_IND_P_X as shown in diagram ??
-- SALS parity checking
-- ?? I have added a latch (FL) on PA to hold it at T4, as are W_IND_P and X_IND_P
-- This keeps WX_CHK valid during T1, T2 and T3 - it is checked during T2 of the following cycle
-- Without this, spurious ROS_ADDR checks are generated because PA is not always valid at the next T2
PA_PH: PH port map(SALS.SALS_PA,T4,PA_LCH);
WX_CHK <= not(PA_LCH xor W_IND_P_X xor X_IND_P_X); -- AA2J4 ?? Inverted ??
sSAL_PC <= not EvenParity(USE_BASIC_CA_DECODER & SALS.SALS_AK & SALS.SALS_PK & SALS.SALS_CH & SALS.SALS_CL &
SALS.SALS_CM & SALS.SALS_CU & SALS.SALS_CA & SALS.SALS_CB & SALS.SALS_CK & SALS.SALS_PA & SALS.SALS_PS)
or
@ -212,7 +216,7 @@ mux(GT_CA_TO_W_REG, (SALS.SALS_AA & SALS.SALS_CA & SALS.SALS_PK)) or -- AA2H2,AA
mux(GT_FWX_TO_WX_REG, FW & FW_P)); -- AA2H2,AA2J2,AA2F2
-- X Reg assembly
sINH_NORM_ENTRY <= '1' when SALS.SALS_CK="0101" and SALS.SALS_AK='1' and CARRY_0_LCHD='1' else '0'; -- AB3H7,AA2F5
sINH_NORM_ENTRY <= '1' when SALS.SALS_CK="0101" and SALS.SALS_AK='1' and CARRY_0_LCHD='1' else '0'; -- AB3H7,AA2F5 CK=0101 AK=1 ACFORCE
X_ASSM <= (
mux(GT_FWX_TO_WX_REG, FX & FX_P) or -- AA2G3
@ -221,7 +225,7 @@ mux(GT_GWX_TO_WX_REG, GX & GX_P) or -- AA2G3
mux(GT_SWS_TO_WX_PWR, SWS_H & SWS_J & SWS_HJP) or -- AA2F3
mux(GT_UV_TO_WX_REG, V & V_P) or -- AA2F3
mux(NORMAL_ENTRY and not sINH_NORM_ENTRY, (SALS.SALS_CN & X6 & X7 & (SALS.SALS_PN xor X6 xor X7))) or -- AA2F3
mux(not SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3) and SALS.SALS_AK and CARRY_0_LCHD ,"000000001") or -- AA2H5
mux(sINH_NORM_ENTRY, "000000001") or -- AA2H5 XP=1 for ACFORCE
mux(ANY_PRIORITY_PULSE_PWR and SEL_CC_ROS_REQ and SX_CHAIN_PULSE, "000000110") or -- AA2H3
mux(HSMPX_TRAP and SX_CHAIN_PULSE, "000001001") -- AA2E7
);
@ -237,19 +241,20 @@ SET_W2A <= not ANY_PRIORITY_PULSE_PWR or not ALU_CHK_LCH or not CHK_SW_PROC_SW;
-- SET_W2A <= '1';
SET_W2B <= sGT_BU_ROSAR_TO_WX_REG or not NORMAL_ENTRY; -- AA2F2
SET_W2 <= SET_W2A and SET_W2B; -- AA2H5,AA2F2 Wired-AND
SET_W_REG <= ((GT_CA_TO_W_REG or GT_CK_TO_W_REG or SET_W2) and P1) or MACH_RST_SET_LCH_DLY; -- AA2D2
SET_W_REG <= ((GT_CA_TO_W_REG or GT_CK_TO_W_REG or SET_W2) and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ??
REG_W: PHV5 port map(W_ASSM(3 to 7),SET_W_REG,sWX(0 to 4)); -- AA2D2
REG_WP: PH port map(W_ASSM(8),SET_W_REG,W_P); -- AA2D2
-- X_LATCH:
SET_X_REG <= (not INH_ROSAR_SET and P1) or MACH_RST_SET_LCH_DLY; -- AA2D2
SET_X_REG <= (not INH_ROSAR_SET and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ??
REG_X: PHV8 port map(X_ASSM(0 to 7),SET_X_REG,sWX(5 to 12)); -- AA2D3
REG_XP: PH port map(X_ASSM(8),SET_X_REG,X_P); -- AA2D3
WX <= sWX;
-- Backup ROSAR regs
SET_F <= (MPX_SHARE_PULSE and T4) or MACH_RST_4; -- AA3G3
SET_F <= (MPX_SHARE_PULSE and T4) or MACH_RST_4; -- AA3G3
SET_FW <= SET_F;
FWX_LCH: PHV13 port map(sWX,SET_F,FWX); -- AA3H2,AA3H3
FWP_LCH: PH port map(W_P,SET_F,FW_P); -- AA3H2
FXP_LCH: PH port map(X_P,SET_F,FX_P); -- AA3H3
@ -266,4 +271,23 @@ GXP_LCH: PH port map(X_P,SET_G,GX_P); -- AA2L2
CROS_GO_PULSE <= T2 and not (CHK_OR_DIAG_STOP_SW and ALLOW_PC_SALS and (sSAL_PC or sCTRL_REG_CHK)); -- AA2E7,AA2E2,AA2C2 ??
CROS_STROBE <= T3; -- AA3L6
with DEBUG.SELECTION select
DEBUG.PROBE <=
FWX(0) when 0,
FWX(1) when 1,
FWX(2) when 2,
FWX(3) when 3,
FWX(4) when 4,
FWX(5) when 5,
FWX(6) when 6,
FWX(7) when 7,
FWX(8) when 8,
FWX(9) when 9,
FWX(10) when 10,
FWX(11) when 11,
FWX(12) when 12,
FW_P when 13,
FX_P when 14,
MPX_SHARE_PULSE when 15;
end FMD;

284
FMD2030_5-01C-D.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Change CCROS initialisation
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -44,6 +44,8 @@ USE std.textio.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
library CCROS;
use CCROS.CCROS.all;
ENTITY CCROS IS
port
@ -74,272 +76,6 @@ END CCROS;
ARCHITECTURE FMD OF CCROS IS
subtype CCROS_Address_Type is integer range 0 to 4095;
subtype CCROS_Word_Type is std_logic_vector(0 to 54);
type CCROS_Type is array(CCROS_Address_Type) of CCROS_Word_Type;
impure function readCCROS return CCROS_Type is
variable fileCCROS : CCROS_Type := (others => (others => '0'));
variable Cline : line;
variable addr : natural;
variable CCROSaddr : CCROS_Address_Type;
file CCROS_lines : text open read_mode is "ccros20100715.txt";
function fmHex(c : in character) return integer is
begin
if (c>='0') and (c<='9') then return character'pos(c)-character'pos('0');
elsif (c>='A') and (c<='F') then return character'pos(c)-character'pos('A')+10;
elsif (c>='a') and (c<='f') then return character'pos(c)-character'pos('a')+10;
else
report "Invalid hex address:" & c severity note;
return 0;
end if;
end;
function fmBin(c : in character) return STD_LOGIC is
begin
if c='0' then return '0';
elsif c='1' then return '1';
elsif c='?' then return '0';
else
report "Invalid bit:" & c severity note;
return '0';
end if;
end;
-- parity() function returns 1 if the vector has even parity
function parity(v : STD_LOGIC_VECTOR) return STD_LOGIC is
variable p : STD_LOGIC;
begin
p := '1';
for i in v'range loop
p := p xor v(i);
end loop;
return p;
end;
function toString(v : STD_LOGIC_VECTOR) return string is
variable s : string(1 to 55);
begin
for i in v'range loop
if v(i)='1' then s(i+1):='1';
else s(i+1):='0'; end if;
end loop;
return s;
end;
variable char : character;
variable field : integer;
variable newC : CCROS_Word_Type;
variable version : string(1 to 3);
variable eol : boolean;
variable cstr3 : string(1 to 3);
variable cstr8 : string(1 to 8);
variable cstr55 : string(1 to 55);
begin
for i in 1 to 8192 loop
exit when endfile(CCROS_lines);
readline(CCROS_lines,Cline);
exit when endfile(CCROS_lines);
-- 1-3 = address (hex)
-- 5-6 = CN hex (ignore 2 lower bits)
-- 8-11 = CH
-- 13-16 = CL
-- 18-20 = CM
-- 22-23 = CU
-- 25-28 = CA
-- 30-31 = CB
-- 33-36 = CK
-- 38-41 = CD
-- 43-45 = CF
-- 47-48 = CG
-- 50-51 = CV
-- 53-55 = CC
-- 57-60 = CS
-- 62 = AA
-- 64 = AS
-- 66 = AK
-- 68 = PK
-- File layout:
-- #AAA CN CH CL CM CU CA CB CK CD CF CG CV CC CS AAASAKPK
read(Cline,char);
if char='#' then next; end if;
addr := fmHex(char);
cstr3(1) := char;
read(Cline,char); addr := addr*16+fmhex(char);
cstr3(2) := char;
read(Cline,char); addr := addr*16+fmhex(char);
cstr3(3) := char;
CCROSaddr := CCROS_Address_Type(addr);
-- report "Addr: " & cstr3 severity note;
-- PN (0) omitted for now
-- CN
-- read(Cline,char); -- 4
read(Cline,char); field := fmHex(char);
read(Cline,char); field := field*16+fmhex(char);
field := field / 4;
newC(1 to 6) := conv_std_logic_vector(field,6);
-- PS (7) and PA (8) omitted for now
-- CH
-- read(Cline,char);
read(Cline,char); newc( 9) := fmBin(char);
read(Cline,char); newc(10) := fmBin(char);
read(Cline,char); newc(11) := fmBin(char);
read(Cline,char); newc(12) := fmBin(char);
-- CL
-- read(Cline,char);
read(Cline,char); newc(13) := fmBin(char);
read(Cline,char); newc(14) := fmBin(char);
read(Cline,char); newc(15) := fmBin(char);
read(Cline,char); newc(16) := fmBin(char);
-- CM
-- read(Cline,char);
read(Cline,char); newc(17) := fmBin(char);
read(Cline,char); newc(18) := fmBin(char);
read(Cline,char); newc(19) := fmBin(char);
-- CU
-- read(Cline,char);
read(Cline,char); newc(20) := fmBin(char);
read(Cline,char); newc(21) := fmBin(char);
-- CA
-- read(Cline,char);
read(Cline,char); newc(22) := fmBin(char);
read(Cline,char); newc(23) := fmBin(char);
read(Cline,char); newc(24) := fmBin(char);
read(Cline,char); newc(25) := fmBin(char);
-- CB
-- read(Cline,char);
read(Cline,char); newc(26) := fmBin(char);
read(Cline,char); newc(27) := fmBin(char);
-- CK
-- read(Cline,char);
read(Cline,char); newc(28) := fmBin(char);
read(Cline,char); newc(29) := fmBin(char);
read(Cline,char); newc(30) := fmBin(char);
read(Cline,char); newc(31) := fmBin(char);
-- PK (32) and PC (33) omitted for now
-- CD
-- read(Cline,char);
read(Cline,char); newc(34) := fmBin(char);
read(Cline,char); newc(35) := fmBin(char);
read(Cline,char); newc(36) := fmBin(char);
read(Cline,char); newc(37) := fmBin(char);
-- CF
-- read(Cline,char);
read(Cline,char); newc(38) := fmBin(char);
read(Cline,char); newc(39) := fmBin(char);
read(Cline,char); newc(40) := fmBin(char);
-- CG
-- read(Cline,char);
read(Cline,char); newc(41) := fmBin(char);
read(Cline,char); newc(42) := fmBin(char);
-- CV
-- read(Cline,char);
read(Cline,char); newc(43) := fmBin(char);
read(Cline,char); newc(44) := fmBin(char);
-- CC
-- read(Cline,char);
read(Cline,char); newc(45) := fmBin(char);
read(Cline,char); newc(46) := fmBin(char);
read(Cline,char); newc(47) := fmBin(char);
-- CS
-- read(Cline,char);
read(Cline,char); newc(48) := fmBin(char);
read(Cline,char); newc(49) := fmBin(char);
read(Cline,char); newc(50) := fmBin(char);
read(Cline,char); newc(51) := fmBin(char);
-- AA
-- read(Cline,char);
read(Cline,char); newc(52) := fmBin(char);
-- AS
-- read(Cline,char);
read(Cline,char); newc(53) := fmBin(char);
-- AK
-- read(Cline,char);
read(Cline,char); newc(54) := fmBin(char);
-- PK
-- read(Cline,char);
read(Cline,char); newc(32) := fmBin(char);
-- Now fill in PN,PA,PS,PC
newc(0) := parity(newc(1 to 6)); -- PN = CN
newc(8) := parity(CONV_STD_LOGIC_VECTOR(CCROSAddr,13)); -- PA = ADDR
-- if (newc(13 to 16)="0010") then
-- newc(32) := parity(newc(22 to 25)); -- PK = CA
-- else
-- newc(32) := parity(newc(28 to 31)); -- PK = CK
-- end if;
newc(7) := parity(newc(8 to 32) & newc(52) & newc(54)); -- PS = PA CH CL CM CU CA CB CK PK AA AK
newc(33) := parity(newc(34 to 51) & newc(53)); -- PC = CD CF CG CV CC CS AS
-- Bodge to generate incorrect parity for some locations
if addr=unsigned'(x"BA0") then -- BA0 has parity change "7" = PS PA PC
-- newc(7) := not newc(7); -- Already doing PA so no need to flip PS
newc(8) := not newc(8); -- PA
newc(33) := not newc(33); -- PC
end if;
if addr=unsigned'(x"B60") then -- B60 has parity change "B" = PN PA PC
newc(0) := not newc(0); -- PN
newc(7) := not newc(7); -- Need to flip PS to keep it correct when PA is flipped
newc(8) := not newc(8); -- PA
newc(33) := not newc(33); -- PC
end if;
-- Skip over page/location
read(Cline,char);read(Cline,cstr8);
-- report "Loc: " & cstr8 severity note;
-- for i in newC'range loop
-- if newC(i)='1' then
-- report "1" severity note;
-- else
-- report "0" severity note;
-- end if;
-- end loop;
-- See if there is a version
read(Cline,char,eol);
read(Cline,version,eol);
if char='-' then
-- report "Version: "&version severity note;
else
version := " ";
end if;
-- Check for acceptable versions
-- 000/Blank = Basic
-- 004 = 64k
-- 005 = 224UCWs
-- 006 = Storage Protect
-- 007 = Decimal Option
-- 010 = 1050 Console
-- 014 = Selector Channel #1
-- 025 = 50Hz timer
-- A20 = 64k + Storage Protect
-- Omitted:
-- 015 = Selector Channel 2
-- 031 = ??
-- 906 = Storage Protect Diagnostic
-- 914 = Selector Channel Diagnostic
-- 994 = ??
-- 995 = Local Storage Dump
-- 996 = Storage Diagnostic
-- 997 = Mpx Diagnostic
if version=" " or version="000" or version="004" or version="005" or version="006" or
version="007" or version="010" or version="014" or version="025" or version="A20" then
if fileCCROS(CCROSaddr) = (newC'range => '0') then
fileCCROS(CCROSaddr) := newC;
else
report "Duplicate CCROS " & integer'image(CCROSAddr) & " Ver " & version severity note;
end if;
else
report "CCROS " & integer'image(CCROSAddr) & " Ver " & version & " skipped" severity note;
end if;
-- report "CCROS " & integer'image(CCROSAddr) & ": " & toString(newC);
end loop;
return fileCCROS;
end;
signal SALS_Word : STD_LOGIC_VECTOR(0 to 54) := (others=>'1');
alias SALS_PN : STD_LOGIC is SALS_Word(0);
@ -365,7 +101,8 @@ alias SALS_AA : STD_LOGIC is SALS_Word(52);
alias SALS_SA : STD_LOGIC is SALS_Word(53);
alias SALS_AK : STD_LOGIC is SALS_Word(54);
constant CCROS : CCROS_Type := readCCROS;
constant CCROS : CCROS_Type := Package_CCROS;
-- constant CCROS : CCROS_Type := readCCROS;
signal AUX_CTRL_REG_RST : STD_LOGIC;
signal SET_CTRL_REG : STD_LOGIC;
@ -376,8 +113,9 @@ signal CD_LCH_Set,CD_LCH_Reset,CS_LCH_Set,CS_LCH_Reset : STD_LOGIC_VECTOR(0 to 3
signal STRAIGHT_LCH_Set,CROSSED_LCH_Set,CC2_LCH_Set,CC2_LCH_Reset,GTAHI_LCH_Set,GTAHI_LCH_Reset,
GTALO_LCH_Set,GTALO_LCH_Reset,COMPCY_LCH_Set,COMPCY_LCH_Reset,CG0_Set,CG1_Set,CG_Reset : STD_LOGIC;
signal CV_LCH_Set,CV_LCH_Reset,CC01_LCH_Set,CC01_LCH_Reset : STD_LOGIC_VECTOR(0 to 1);
signal CROS_STROBE_DELAY : STD_LOGIC_VECTOR(1 to 5) := "00000";
signal CROS_STROBE_DELAY : STD_LOGIC_VECTOR(1 to 6) := "000000";
BEGIN
-- Page 5-01C
sCTRL_REG_RST <= MACH_RST_SW or MANUAL_STORE or ANY_PRIORITY_LCH;
CTRL_REG_RST <= sCTRL_REG_RST;
@ -440,11 +178,11 @@ begin
-- if (CROS_STROBE='1' and CROS_STROBE_DELAY="10000") then
--SALS_Word <= (others => '0');
-- else
if (CROS_STROBE='1' and CROS_STROBE_DELAY="11110") then
if (CROS_STROBE='1' and CROS_STROBE_DELAY="111100") then
SALS_Word <= CCROS(CCROS_Address_Type(conv_integer(unsigned(WX(1 to 12)))));
-- end if;
end if;
CROS_STROBE_DELAY <= CROS_STROBE & CROS_STROBE_DELAY(1 to 4);
CROS_STROBE_DELAY <= CROS_STROBE & CROS_STROBE_DELAY(1 to 5);
end if;
end process;

8
FMD2030_5-02A-B.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Enable MPX interruptions
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -149,7 +149,7 @@ DEBUG <= ASCII_LCH;
-- ?? Debug remove other interrupt sources
-- sINTERRUPT <= TIMER_UPDATE or EXTERNAL_INT or MPX_INTERRUPT or SX1_INTERRUPT or SX2_INTERRUPT; -- AA3K4
sINTERRUPT <= EXTERNAL_INT;
sINTERRUPT <= EXTERNAL_INT or MPX_INTERRUPT;
INTERRUPT <= sINTERRUPT;

14
FMD2030_5-03A.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Change Priority Reset latch signal name
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -152,7 +152,7 @@ signal sMACH_CHK_PULSE : STD_LOGIC;
signal sFORCE_IJ_PULSE : STD_LOGIC;
signal sANY_PRIORITY_PULSE : STD_LOGIC;
signal sMPX_SHARE_PULSE : STD_LOGIC;
signal SUPPR_MACH_TRAP_L,PRIOR_RST_Reset,MEMP_LCH_Set,MEMP_LCH_Reset,PRI_LCH_Set,
signal SUPPR_MACH_TRAP_L,PRIOR_RST_Latch,MEMP_LCH_Set,MEMP_LCH_Reset,PRI_LCH_Set,
PRI_LCH_Reset,PRISTK_LCH_Latch : STD_LOGIC;
BEGIN
@ -170,8 +170,8 @@ S1_DLYD: PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2
WX_SABC: PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2
GT_SW_TO_WX_LCH <= sGT_SW_TO_WX_LCH;
CD0101 <= '1' when SALS_CDREG="0101" else '0';
PRIOR_RST_Reset <= T4 or MACH_RST_SW;
PRIOR_RST_CTRL_PH: PHR port map(CD0101,PRIOR_RST_Reset,sANY_PRIORITY_PULSE,PRIOR_RST_CTRL); -- AB3J2
PRIOR_RST_Latch <= T4 or MACH_RST_SW;
PRIOR_RST_CTRL_PH: PHR port map(D=>CD0101,L=>PRIOR_RST_Latch,R=>sANY_PRIORITY_PULSE,Q=>PRIOR_RST_CTRL); -- AB3J2
MEMP_LCH_Set <= sDATA_READY and ALLOW_PROTECT and PROT_LOC_CPU_OR_MPX;
MEMP_LCH_Reset <= READ_CALL or RECYCLE_RST;
STG_PROT_REQ: FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7
@ -186,7 +186,7 @@ DATA_READY <= sDATA_READY;
PRI_LCH_Set <= (T1 and DIAGNOSTIC_SW) or MACH_RST_LCH or (not HARD_STOP_LCH and T3 and sANY_PRIORITY_LCH);
PRI_LCH_Reset <= sHZ_DEST_RST or sGT_SW_MACH_RST;
PRIORITY: FLL port map(PRI_LCH_Set,PRI_LCH_Reset,PRIORITY_LCH); -- AB3J4,AB3L4
PRIORITY: FLL port map(S=>PRI_LCH_Set,R=>PRI_LCH_Reset,Q=>PRIORITY_LCH); -- AB3J4,AB3L4
-- Priority stack register - all inputs are inverted AB3L2
PRIORITY_STACK_IN(0) <= GT_SWS_TO_WX_PWR;

13
FMD2030_5-03B.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,9 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Reset UMPX latch on RECYCLE_RST
-- Change to 64k wrap
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -119,7 +120,7 @@ UWRAP_LCH_Reset <= RECYCLE_RST or RESET_WRAP;
UWRAP_LCH: PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4
IWRAP_LCH: PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4
I_WRAPPED_CPU <= sI_WRAPPED_CPU;
UMPX_LCH: PH port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,Q=>sU_WRAPPED_MPX); -- AB2M4
UMPX_LCH: PHR port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,R=>RECYCLE_RST,Q=>sU_WRAPPED_MPX); -- AB2M4 ?? Doesn't have reset in FMD - causes Diag failure
U_WRAPPED_MPX <= sU_WRAPPED_MPX;
WBUFF_LCH: PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ??
@ -128,10 +129,10 @@ WRAP64 <= (not H_REG_6 and GT_V_TO_N_REG and U_WRAP_CPU) or
(GT_V_TO_N_REG and H_REG_6 and sU_WRAPPED_MPX);
-- Select the appropriate wrap condition based on storage size:
sMEM_WRAP <= M012(0) or M012(1) or M012(2); -- 8k
-- sMEM_WRAP <= M012(0) or M012(1) or M012(2); -- 8k
-- sMEM_WRAP <= M012(0) or M012(1); -- 16k
-- sMEM_WRAP <= M012(0); -- 32k
-- sMEM_WRAP <= WRAP64; -- 64k
sMEM_WRAP <= WRAP64; -- 64k
MEM_WRAP <= sMEM_WRAP;
MWR_LCH_Set <= MAIN_STORAGE and T2 and (sMEM_WRAP and not ALLOW_WRITE); -- ?? ALLOW_WRITE use unclear - dot logic

9
FMD2030_5-03C.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Change PROC_STOP_LOOP condition to make STOP/START buttons happier
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -221,7 +221,8 @@ PS_LCH_Set <= sSET_IC_ALLOWED or SW_STOP or (SAR_DLYD_STOP_SW and MATCH) or (INS
PS_LCH_Reset <= sSTART_SW_RST or '0'; -- ?? What is second reset input?
PS_LCH: FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5
DEBUG <= PROCESS_STOP; -- ?? DEBUG ??
PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed??
-- PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed??
PROC_STOP_LOOP_ACTIVE <= ((USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed?? and inverter on AA2G5 removed??
INH_ROSAR_SET <= PROC_STOP_LOOP_ACTIVE and not ANY_PRIORITY_PULSE; -- AC1D5
STOP_REQ <= PROCESS_STOP and not S_REG_1_DLYD and not INTERRUPT and END_OF_E_CY_LCH; -- AC1H7
-- CF STOP

8
FMD2030_5-04C.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.01 2012-04-07
-- Fix typo in comment
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -166,7 +166,7 @@ CNTR_FULL <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BI
sTIMER_UPDATE <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6,BE3G5
TIMER_UPDATE <= sTIMER_UPDATE;
-- TIMER_UPDATE_OR_EXT_INT <= sTIMER_UPDATE or EXT_INT; -- AC1D5
TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporary prevent Timer
TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporarily prevent Timer
EXT_INT <= (F_REGISTER(0) or F_REGISTER(1) or F_REGISTER(2) or F_REGISTER(3) or
F_REGISTER(4) or F_REGISTER(5) or F_REGISTER(6) or F_REGISTER(7)) and EXT_TRAP_MASK_ON; -- AC1G2 ?? Should this include EXT_TRAP_MASK_ON ?
EI_LCH_Reset <= MACH_RST_SW or RESET_F_REG;

13
FMD2030_5-05D.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Changed for 64k storage: START_1ST_32K triggered for 1st *and* 2nd 32k
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -84,7 +84,7 @@ END RWStgClk1st32k;
ARCHITECTURE FMD OF RWStgClk1st32k IS
signal START_RD,START_WR : STD_LOGIC;
signal START_1ST_32K : STD_LOGIC;
signal START_1ST_32K, START_2ND_32K : STD_LOGIC;
signal READ_CALL_TO_MEM,WRITE_CALL_TO_MEM : STD_LOGIC;
signal sREAD_CALL : STD_LOGIC;
signal sUSE_LOCAL_MAIN_MEM : STD_LOGIC;
@ -123,8 +123,9 @@ USE_LOCAL: FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- C
USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM;
USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2
START_1ST_32K <= (not EARLY_M_REG_0 and READ_CALL_TO_MEM) or (READ_CALL_TO_MEM and EARLY_LOCAL_STG) or (not M_REG_0 and WRITE_CALL_TO_MEM) or (WRITE_CALL_TO_MEM and sUSE_LOCAL_MAIN_MEM); -- CB1E2
-- START_2ND_32K <= (READ_CALL_TO_MEM and EARLY_M_REG_0 and not sUSE_LOCAL_MAIN_MEM) or (WRITE_CALL_TO_MEM and M_REG_0 and not sUSE_LOCAL_MAIN_MEM); -- CB1E2
-- START_1ST_32K <= (not EARLY_M_REG_0 and READ_CALL_TO_MEM) or (READ_CALL_TO_MEM and EARLY_LOCAL_STG) or (not M_REG_0 and WRITE_CALL_TO_MEM) or (WRITE_CALL_TO_MEM and sUSE_LOCAL_MAIN_MEM); -- CB1E2
-- START_2ND_32K <= (READ_CALL_TO_MEM and EARLY_M_REG_0 and not sUSE_LOCAL_MAIN_MEM) or (WRITE_CALL_TO_MEM and M_REG_0 and not sUSE_LOCAL_MAIN_MEM); -- CB1E2
START_1ST_32K <= READ_CALL_TO_MEM or WRITE_CALL_TO_MEM; -- CB1E2 combined 1st & 2nd 32k
-- Generate timing signals relative to START_xxx_32K
-- READ_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)

80
FMD2030_5-06C-D.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Implement external 64k + aux storage using StorageIn / StorageOut
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -107,6 +107,10 @@ ENTITY RREG_STG IS
ALLOW_PROTECT : OUT STD_LOGIC; -- 03A7
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
-- Interface to hardware
StorageIn : IN STORAGE_IN_INTERFACE;
StorageOut : OUT STORAGE_OUT_INTERFACE;
-- Clocks
-- P3 : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
@ -117,7 +121,8 @@ END RREG_STG;
ARCHITECTURE FMD OF RREG_STG IS
TYPE MAIN_STG_TYPE is ARRAY(0 to 8191) of STD_LOGIC_VECTOR(0 to 8);
TYPE MAIN_STG_TYPE is ARRAY(0 to 1023) of STD_LOGIC_VECTOR(0 to 8);
-- TYPE MAIN_STG_TYPE is ARRAY(0 to 8191) of STD_LOGIC_VECTOR(0 to 8);
TYPE LOCAL_STG_TYPE is ARRAY(0 to 511) of STD_LOGIC_VECTOR(0 to 8);
SIGNAL SX1_STOR,SX2_STOR : STD_LOGIC;
@ -137,17 +142,7 @@ SIGNAL sALLOW_PROTECT : STD_LOGIC;
signal sSTORE_BITS : STD_LOGIC_VECTOR(0 to 8);
signal SX1_STOR_INPUT_DATA_Set,SX1_STOR_INPUT_DATA_Reset,SX2_STOR_INPUT_DATA_Set,SX2_STOR_INPUT_DATA_Reset,
PROT_MEM_Set,PROT_MEM_Reset,P_8F_DETECT_Set,P_8F_DETECT_Reset : STD_LOGIC;
SIGNAL LOCAL_STG_ARRAY : LOCAL_STG_TYPE := (
336 => "000000001",
337 => "000000001",
338 => "000000001",
339 => "010111010", -- R5 = 0000005D
368 => "000000001",
369 => "000000001",
370 => "000000001",
371 => "100110011", -- R7 = 00000099
others => "000000001"
);
SIGNAL LOCAL_STG_ARRAY : LOCAL_STG_TYPE;
SIGNAL MAIN_STG_ARRAY : MAIN_STG_TYPE := (
16#000# => "000000001", -- 00
16#001# => "000000010", -- 01
@ -325,28 +320,37 @@ P_8F_DETECT_Set <= STORAGE_BUS(0) and MAIN_STG and N1401_MODE and DET0F;
P_8F_DETECT_Reset <= MACH_RST_SW or GMWM_DETECTED;
P_8F_DETECT: FLL port map(P_8F_DETECT_Set,P_8F_DETECT_Reset,P_8F_DETECTED); -- AA1F5
STG_Wr: process (PHASE_WR_1)
begin
if (PHASE_WR_1'EVENT AND PHASE_WR_1='1') then
if (USE_MAIN_MEM='1') then
MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15)))) <= sSTORE_BITS;
else
LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15)))) <= sSTORE_BITS;
end if;
end if;
end process;
STG_Rd: process (PHASE_RD_1,USE_MAIN_MEM,MAIN_STG_ARRAY,LOCAL_STG_ARRAY,MN)
begin
if (PHASE_RD_1='1') then
if (USE_MAIN_MEM='1') then
STORAGE_BUS <= MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15))));
else
STORAGE_BUS <= LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15))));
end if;
else
STORAGE_BUS <= "000000000";
end if;
end process;
StorageOut.WriteData <= sSTORE_BITS;
StorageOut.MainStorage <= USE_MAIN_MEM;
StorageOut.ReadPulse <= PHASE_RD_1 and not DATA_READY; -- Drop ReadPulse when Data Ready goes active, this will latch input data
StorageOut.WritePulse <= PHASE_WR_1;
StorageOut.MSAR <= MN;
STORAGE_BUS <= StorageIn.ReadData when PHASE_RD_1='1' else "000000000"; -- Data is retained a bit after DATA_READY falls
STG_Wr: process (PHASE_WR_1)
begin
if (PHASE_WR_1'EVENT AND PHASE_WR_1='1') then
if (USE_MAIN_MEM='1') then
-- MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15)))) <= sSTORE_BITS;
else
-- LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15)))) <= sSTORE_BITS;
end if;
end if;
end process;
STG_Rd: process (PHASE_RD_1,USE_MAIN_MEM,MAIN_STG_ARRAY,LOCAL_STG_ARRAY,MN,StorageIn.ReadData)
begin
if (PHASE_RD_1='1') then
if (USE_MAIN_MEM='1') then
-- STORAGE_BUS <= StorageIn.ReadData;
-- STORAGE_BUS <= MAIN_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3 to 15))));
else
-- STORAGE_BUS <= StorageIn.ReadData;
-- STORAGE_BUS <= LOCAL_STG_ARRAY(TO_INTEGER(UNSIGNED(MN(3) & MN(8 to 15))));
end if;
else
-- STORAGE_BUS <= "000000000";
end if;
end process;
END FMD;

13
FMD2030_5-07B2.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Change GT_CS_OPT to level-triggered latch
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -98,7 +98,8 @@ CS_0XXX <= '1' when CS(0)='0' else '0';
CS_1XXX <= '1' when CS(0)='1' else '0';
GT_CS_OPT_Set <= SA and P1;
GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
-- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
GT_CS_OPT: FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5
GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
@ -131,7 +132,7 @@ RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0
RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS);
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS);
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
END FMD;

137
FMD2030_5-07B_2.vhd Normal file
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@ -0,0 +1,137 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B_2.vhd
-- Creation Date: 01/11/09
-- Description:
-- S Register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY SReg IS
port
(
SA : IN STD_LOGIC; -- 01C
CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B
GT_CARRY_TO_S3 : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(0 to 7);
GT_Z_BUS_TO_S : OUT STD_LOGIC;
S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC; -- 01C
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
STORE_S_REG_RST : IN STD_LOGIC; -- 03D
E_SW_SEL_S : IN STD_LOGIC; -- 04C
MACH_RST_2C : IN STD_LOGIC; -- 06B
T_REQUEST : IN STD_LOGIC; -- 10BC6
FB_K_T2_PULSE : OUT STD_LOGIC;
CS_DECODE_X001 : OUT STD_LOGIC; -- 03C
BASIC_CS_0 : OUT STD_LOGIC; -- 03C
P1, T1, T2, T3, T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END SReg;
ARCHITECTURE FMD OF SReg IS
signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7);
signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC;
signal CD_0110 : STD_LOGIC;
signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC;
signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC;
signal sGT_Z_BUS_TO_S : STD_LOGIC;
signal sS_REG_RST : STD_LOGIC;
signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC;
signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-07B
CS_X000 <= '1' when CS(1 to 3)="000" else '0';
CS_X001 <= '1' when CS(1 to 3)="001" else '0';
CS_DECODE_X001 <= CS_X001;
CS_X010 <= '1' when CS(1 to 3)="010" else '0';
CS_X011 <= '1' when CS(1 to 3)="011" else '0';
CS_X100 <= '1' when CS(1 to 3)="100" else '0';
CS_X101 <= '1' when CS(1 to 3)="101" else '0';
CS_X110 <= '1' when CS(1 to 3)="110" else '0';
CS_X111 <= '1' when CS(1 to 3)="111" else '0';
CS_X01X <= '1' when CS(1 to 2)="01" else '0';
CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0';
CS_0XXX <= '1' when CS(0)='0' else '0';
CS_1XXX <= '1' when CS(0)='1' else '0';
GT_CS_OPT_Set <= SA and P1;
GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
BASIC_CS_0 <= sBASIC_CS_0;
FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3
CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6
sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S;
sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
S_REG_RST <= sS_REG_RST;
SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7
SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7
SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7
SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7
SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7
SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7
SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7
SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7
RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7
RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7
RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7
RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7
RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS);
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS);
S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
END FMD;

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@ -0,0 +1,171 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer: LJW
--
-- Create Date: 22:26:31 04/18/05
-- Design Name:
-- Module Name: Clock+MpxInd - Behavioral
-- Project Name: IBM2030
-- Target Device: XC3S1000
-- Tool versions: ISE V7.1
-- Description: Four-phase clock generation and Multiplexor channel indicators
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ClockMpxInd is Port (
-- Clock stuff
CLOCK_IN : in std_logic;
T1,T2,T3,T4 : out std_logic;
P1,P2,P3,P4 : out std_logic;
OSC_T_LINE : out std_logic; -- 12A
M_CONV_OSC : out std_logic; -- 03C
P_CONV_OSC : out std_logic; -- 03D,03C
M_CONV_OSC_2 : out std_logic; -- 03C
CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B
CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D
CLOCK_START : in std_logic; -- 03C
MACH_RST_3 : in std_logic; -- 03D
-- Mpx Indicator stuff
TEST_LAMP : in std_Logic; -- 04A
OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN,
SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT,
SUPPRESS_OUT : in std_logic; -- 08D
FO_P : in std_logic; -- 08C
FO : in std_logic_vector(0 to 7); -- 08C
IND_OPNL_IN, IND_ADDR_IN,IND_STATUS_IN,IND_SERV_IN,
IND_SEL_OUT,IND_ADDR_OUT,IND_CMMD_OUT,IND_SERV_OUT,
IND_SUPPR_OUT,IND_FO_P : out std_logic;
IND_FO : out std_logic_vector(0 to 7)
);
end ClockMpxInd;
architecture slt of ClockMpxInd is
-- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0);
-- constant RATIO : DividerSize := "001111"; -- 16 gives 3.125MHz
-- subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0);
-- constant RATIO : DividerSize := "00111100000000000000000000"; -- 16M gives 3.125Hz
subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0);
constant RATIO : DividerSize := "00010011000100101101000000"; -- 5M gives 10Hz
constant ZERO : DividerSize := (others=>'0');
constant ONE : DividerSize := (0=>'1',others=>'0');
signal DIVIDER : DividerSize;
signal OSC2,OSC,DLYD_OSC : STD_LOGIC;
-- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4);
signal CLK : STD_LOGIC_VECTOR(1 to 4);
begin
-- Divide the 50MHz FPGA clock down
-- 1.5us storage cycle means T1-4 takes 750ns, or 3MHz
-- OSC2 is actually double the original oscillator as only one edge is used
process (CLOCK_IN)
begin
if CLOCK_IN'event and CLOCK_IN='1' then
if DIVIDER=RATIO then
DIVIDER <= ZERO;
OSC2 <= not OSC2;
else
DIVIDER <= DIVIDER + ONE;
end if;
end if;
end process;
-- AC1K6,AC1C6 Probably have to re-do this lot to get it work
--SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4);
--SETS(2) <= DLYD_OSC not CLK(4) and CLK(1);
--SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2);
--SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1';
--RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1';
--RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1';
--RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1';
--RSTS(4) <= OSC and CLK(1);
--FLV(SETS,RSTS,CLK); -- AC1C6
-- The following process forms a ring counter
-- MACH_RST_3 forces the counter to 0001
-- If CLOCK_START is false, the counter stays at 0001
-- When CLOCK_START goes true, the counter cycles through
-- 0001 0001 0001 1001 1100 0110 0011 1001 1100 ....
-- When CLOCK_START subsequently goes false, the sequence continues
-- until reaching 0011, after which it stays at 0001
-- ... 1001 1100 0110 0011 0001 0001 0001 ...
-- The original counter used a level-triggered implementation, driven by
-- both levels of the OSC signal. Here it is easier to make it edge triggered
-- which requires a clock of twice the frequency, hence OSC2
process (OSC2, MACH_RST_3)
begin
if OSC2'event and OSC2='1' then
if OSC='0' then -- Rising edge
OSC <= '1';
if CLK(2)='1' or MACH_RST_3='1' then
CLK(1) <= '0';
elsif CLOCK_START='1' and CLK(4)='1' then
CLK(1) <= '1';
end if;
if CLK(4)='1' or MACH_RST_3='1' then
CLK(3) <= '0';
elsif CLK(2)='1' then
CLK(3) <= '1';
end if;
else -- Falling edge
OSC <= '0';
if CLK(3)='1' or MACH_RST_3='1' then
CLK(2) <= '0';
elsif CLK(1)='1' then
CLK(2) <= '1';
end if;
if CLK(3)='1' or MACH_RST_3='1' then
CLK(4) <= '1';
elsif CLK(1)='1' then
CLK(4) <= '0';
end if;
end if;
end if;
end process;
OSC_T_LINE <= not OSC;
M_CONV_OSC <= OSC;
DLYD_OSC <= OSC; -- AC1C6
P1 <= CLK(1);
P2 <= CLK(2);
P3 <= CLK(3);
P4 <= CLK(4);
T1 <= CLK(4) and CLK(1);
T2 <= CLK(1) and CLK(2);
T3 <= CLK(2) and CLK(3);
T4 <= CLK(3) and CLK(4);
CLOCK_ON <= CLK(1) or CLK(2) or CLK(3);
CLOCK_OFF <= not (CLK(1) or CLK(2) or CLK(3));
P_CONV_OSC <= OSC and not (CLK(1) or CLK(2) or CLK(3));
M_CONV_OSC_2 <= OSC and not (CLK(1) or CLK(2) or CLK(3)); -- Note: Not inverted, despite the name
-- The indicator drivers for the Multiplexor channel are here
IND_OPNL_IN <= OPNL_IN or TEST_LAMP;
IND_ADDR_IN <= ADDR_IN or TEST_LAMP;
IND_STATUS_IN <= STATUS_IN or TEST_LAMP;
IND_SERV_IN <= SERVICE_IN or TEST_LAMP;
IND_SEL_OUT <= SELECT_OUT or TEST_LAMP;
IND_ADDR_OUT <= ADDR_OUT or TEST_LAMP;
IND_CMMD_OUT <= COMMAND_OUT or TEST_LAMP;
IND_SERV_OUT <= SERVICE_OUT or TEST_LAMP;
IND_SUPPR_OUT <= SUPPRESS_OUT or TEST_LAMP;
IND_FO_P <= FO_P or TEST_LAMP;
IND_FO <= FO or (FO'range => TEST_LAMP);
end slt;

61
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,10 +33,12 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Add registers to all clock outputs and delay rising edge of Px and Tx clocks
---------------------------------------------------------------------------
library IEEE;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
@ -73,7 +75,9 @@ signal DIVIDER : DividerSize := (others=>'0');
signal DIVIDER_MAX : DividerSize;
signal OSC2,OSC,M_DLYD_OSC,DLYN_OSC,T1A,T2A,T3A,T4A,OSC2_DLYD : STD_LOGIC := '0';
-- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4);
signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001";
signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001";
signal P1D,P2D,P3D,P4D : STD_LOGIC;
signal OSC_T_LINEA, CLOCK_ONA, CLOCK_OFFA, P_CONV_OSCA,M_CONV_OSC_2A : STD_LOGIC;
begin
-- Divide the 50MHz FPGA clock down
@ -148,24 +152,43 @@ process (OSC2, MACH_RST_3, CLOCK_START)
end if;
end process;
OSC_T_LINE <= OSC; -- AC1B6
M_CONV_OSC <= not OSC; -- AC1C6
OSC_T_LINEA <= OSC; -- AC1B6
OSC_T_LINED : FDCE port map(D=>OSC_T_LINEA,Q=>OSC_T_LINE,CE=>'1',C=>CLOCK_IN);
M_CONV_OSCD : FDCE port map(D=>not OSC,Q=>M_CONV_OSC,CE=>'1',C=>CLOCK_IN); -- AC1C6
M_DLYD_OSC <= not OSC; -- AC1C6
DLYN_OSC <= OSC; -- AC1C6
P1 <= CLK(1);
P2 <= CLK(2);
P3 <= CLK(3);
P4 <= CLK(4);
T1 <= CLK(4) and CLK(1);
T2 <= CLK(1) and CLK(2);
T3 <= CLK(2) and CLK(3);
T4 <= CLK(3) and CLK(4);
-- P1 <= CLK(1);
-- P2 <= CLK(2);
-- P3 <= CLK(3);
-- P4 <= CLK(4);
-- Delay the rising edge of each P pulse to ensure that the T pulses never overlap
P1DLY: entity DelayRisingEdgeX port map (D=>CLK(1),CLK=>CLOCK_IN,Q=>P1D);
P2DLY: entity DelayRisingEdgeX port map (D=>CLK(2),CLK=>CLOCK_IN,Q=>P2D);
P3DLY: entity DelayRisingEdgeX port map (D=>CLK(3),CLK=>CLOCK_IN,Q=>P3D);
P4DLY: entity DelayRisingEdgeX port map (D=>CLK(4),CLK=>CLOCK_IN,Q=>P4D);
T1A <= P4D and P1D;
T2A <= P1D and P2D;
T3A <= P2D and P3D;
T4A <= P3D and P4D;
T1D : FDCE port map(D=>T1A,Q=>T1,CE=>'1',C=>CLOCK_IN);
T2D : FDCE port map(D=>T2A,Q=>T2,CE=>'1',C=>CLOCK_IN);
T3D : FDCE port map(D=>T3A,Q=>T3,CE=>'1',C=>CLOCK_IN);
T4D : FDCE port map(D=>T4A,Q=>T4,CE=>'1',C=>CLOCK_IN);
P1C : FDCE port map(D=>P1D,Q=>P1,CE=>'1',C=>CLOCK_IN);
P2C : FDCE port map(D=>P2D,Q=>P2,CE=>'1',C=>CLOCK_IN);
P3C : FDCE port map(D=>P3D,Q=>P3,CE=>'1',C=>CLOCK_IN);
P4C : FDCE port map(D=>P4D,Q=>P4,CE=>'1',C=>CLOCK_IN);
CLOCK_ON <= CLK(1) or CLK(2) or CLK(3);
CLOCK_OFF <= not (CLK(1) or CLK(2) or CLK(3));
P_CONV_OSC <= OSC and not (CLK(1) or CLK(2) or CLK(3));
M_CONV_OSC_2 <= not(OSC and not (CLK(1) or CLK(2) or CLK(3)));
CLOCK_ONA <= CLK(1) or CLK(2) or CLK(3);
CLOCK_OND : FDCE port map(D=>CLOCK_ONA,Q=>CLOCK_ON,CE=>'1',C=>CLOCK_IN);
CLOCK_OFFA <= not CLOCK_ONA;
CLOCK_OFFD : FDCE port map(D=>CLOCK_OFFA,Q=>CLOCK_OFF,CE=>'1',C=>CLOCK_IN);
P_CONV_OSCA <= OSC and CLOCK_OFFA;
P_CONV_OSCD : FDCE port map(D=>P_CONV_OSCA,Q=>P_CONV_OSC,CE=>'1',C=>CLOCK_IN);
M_CONV_OSC_2A <= not(P_CONV_OSCA);
M_CONV_OSC_2D : FDCE port map(D=>M_CONV_OSC_2A,Q=>M_CONV_OSC_2,CE=>'1',C=>CLOCK_IN);
end FMD;

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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Revise XH & XL BU latches amd MPX_INTRPT signal
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@ -85,7 +85,7 @@ signal CK11XX, CKX11X,CKX1X1,CK1X1X,CKXX11 : STD_LOGIC;
signal CHNL_L,OPN_L,SUPPR_L,OUT_L : STD_LOGIC;
signal notOP_OUT_SIG,MpxMask : STD_LOGIC;
alias KP is PK_SALS;
signal sFAK,sSET_BUS_O_CTRL,ResetBusO : STD_LOGIC;
signal sFAK,sSET_BUS_O_CTRL : STD_LOGIC;
signal BusO_Set,BusO_Reset : STD_LOGIC_VECTOR (0 to 8);
signal sFT_7_BIT_MPX_CHNL_INTRP,sFT_2_BIT_MPX_OPN_LCH,sSUPPR_CTRL_LCH : STD_LOGIC;
begin
@ -99,12 +99,14 @@ XXH_PH: entity PH port map (D=>XXH_IN, L=>X_SET, Q=> sXXH);
XXH <= sXXH;
XH_BU: entity PH port map (D=>sXH, L=>SET_FW, Q=> XHBU);
XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH);
-- XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH);
XH_IN <= (XHBU and MPX_ROS_LCH) or (S_REG_1 and not MPX_ROS_LCH);
XH_PH: entity PH port map (D=>XH_IN, L=>X_SET, Q=>sXH);
XH <= sXH;
XL_BU: entity PH port map (D=>sXL, L=>SET_FW, Q=> XLBU);
XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH);
-- XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH);
XL_IN <= (XLBU and MPX_ROS_LCH) or (S_REG_2 and not MPX_ROS_LCH);
XL_PH: entity PH port map (D=>XL_IN, L=>X_SET, Q=>sXL);
XL <= sXL;
@ -140,7 +142,7 @@ MPX_OPN_LT_GATE <= CKX11X;
-- ?? Should the R_REG bits be inverted before use?
CKXX11 <= CK_SALS(2) and CK_SALS(3) and FBK_T2;
MPX_MASK: entity PH port map (D=>R_REG(0),L=>CKXX11,Q=>MPXMask);
MPX_INTRPT <= not (sFT_7_BIT_MPX_CHNL_INTRP and MPXMask);
MPX_INTRPT <= sFT_7_BIT_MPX_CHNL_INTRP and MPXMask;
SX1MASK: entity PH port map (D=>R_REG(1),L=>CKXX11,Q=>SX1_MASK);
EXT_MASK: entity PH port map (D=>R_REG(7),L=>CKXX11,Q=>EXT_TRAP_MASK_ON);
SX2MASK: entity PH port map (D=>R_REG(2),L=>CKXX11,Q=>SX2_MASK);

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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,8 +33,8 @@
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Revise Mpx and 1050 signals
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@ -46,10 +46,13 @@ USE work.Buses_package.all;
entity MpxFA is
Port ( BUS_O_REG : in STD_LOGIC_VECTOR (0 to 8);
DIAG_SW : in STD_LOGIC;
-- External MPX connections:
MPX_BUS_OUT_BITS : out STD_LOGIC_VECTOR (0 to 8);
MPX_BUS_IN_BITS : in STD_LOGIC_VECTOR (0 to 8);
TAGS_OUT : out MPX_TAGS_OUT;
TAGS_IN : in MPX_TAGS_IN;
--
FI : out STD_LOGIC_VECTOR(0 to 8); -- Mpx Bus In to CPU
FAK : in STD_LOGIC;
RECYCLE_RST : in STD_LOGIC;
CK_P_BIT : in STD_LOGIC;
@ -75,18 +78,15 @@ entity MpxFA is
LOAD_IND : in STD_LOGIC;
SUPPR_CTRL_LCH : in STD_LOGIC;
OP_OUT_SIGNAL : in STD_LOGIC;
RECYCLE_RESET : in STD_LOGIC;
-- COMMD_OUT : out STD_LOGIC;
-- SERV_OUT : out STD_LOGIC;
OP_OUT_SIG : in STD_LOGIC;
SEL_O_FT6 : out STD_LOGIC;
N1050_SEL_IN : in STD_LOGIC;
N1050_SEL_OUT : out STD_LOGIC;
N1050_SEL_O : in STD_LOGIC;
N1050_SEL_IN : out STD_LOGIC;
n1050_SEL_O : in STD_LOGIC;
P_1050_SEL_IN : out STD_LOGIC;
P_1050_SEL_OUT : out STD_LOGIC;
N1050_INSTALLED : in STD_LOGIC;
SUPPR_O : out STD_LOGIC;
SUPPR_O_FT0 : out STD_LOGIC;
OP_OUT : out STD_LOGIC;
DEBUG : inout DEBUG_BUS;
METERING_OUT : in STD_LOGIC;
CLOCK_OUT : in STD_LOGIC;
CLK : in STD_LOGIC;
@ -105,11 +105,12 @@ signal SERV_OUT, CMD_OUT : STD_LOGIC;
signal sTAGS_OUT : MPX_TAGS_OUT;
signal sTAGS_IN : MPX_TAGS_IN;
signal sFT5_BIT_SEL_IN, Reset_SELO : STD_LOGIC;
signal sN1050_SEL_OUT : STD_LOGIC;
signal sn1050_SEL_OUT : STD_LOGIC;
signal sn1050_SEL_IN : STD_LOGIC;
signal CMD_STT_Set, RST_CMD_RSTT_ADDR_OUT, CMD_STT : STD_LOGIC;
signal sFT3_BIT_MPX_SHARE_REQ, sSEL_O_FT6, sSUPPR_O_FT0 : STD_LOGIC;
signal FAK_T2 : STD_LOGIC;
signal SetAdrO2, ADDR_OUT_2, SetAdrO1, SetCmdO, RstCmdO, SetSrvO, RstSrvO : STD_LOGIC;
signal SetAdrO2, ADDR_OUT_2, SetAdrOut, SetCmdO, RstCmdO, SetSrvO, RstSrvO : STD_LOGIC;
signal SetCUBusyInlk, ResetCUBusyInlk, CUBusy, RST_STT_SEL_OUT : STD_LOGIC;
signal ResetBusOCtrl, BUSOCtrl : STD_LOGIC;
signal SetStartSelO, ResetStartSelO, StartSelO : STD_LOGIC;
@ -124,22 +125,24 @@ ADDR_IN <= sTAGS_IN.ADR_IN; -- AA3F3
OPNL_IN <= sTAGS_IN.OPL_IN; -- AA3F2 AA3F5
SIS1 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.SRV_IN) or OP_INLK; -- AA3F2 AA3E2
sSERV_IN_SIGNAL <= SIS1 and not sTAGS_IN.STA_IN; -- Wire-AND
sSERV_IN_SIGNAL <= SIS1 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit
SERV_IN_SIGNAL <= sSERV_IN_SIGNAL;
SIS3 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.STA_IN) or (OP_INLK and not sTAGS_OUT.ADR_OUT); -- AA3D7 AA3E2
sSTATUS_IN_SIGNAL <= SIS3 and not sTAGS_IN.SRV_IN; -- Wire-AND
sSTATUS_IN_SIGNAL <= SIS3 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit
STATUS_IN_SIGNAL <= sSTATUS_IN_SIGNAL;
OP_INLK_SET <= not sTAGS_IN.OPL_IN and T2;
OP_INLK_FL: entity FLL port map (S=>OP_INLK_SET, R=> T1, Q=>OP_INLK); -- AA3E4 ?? R=> NOT T1 ??
sFT5_BIT_SEL_IN <= (N1050_SEL_IN and not N1050_INSTALLED) or N1050_SEL_IN; -- AA3E5 AA3E2
sn1050_SEL_IN <= sTAGS_IN.SEL_IN;
n1050_SEL_IN <= sn1050_SEL_IN;
sFT5_BIT_SEL_IN <= (sn1050_SEL_IN and not n1050_INSTALLED) or sn1050_SEL_IN; -- AA3E5 AA3E2
FT5_BIT_SEL_IN <= sFT5_BIT_SEL_IN;
Reset_SELO <= RECYCLE_RST or FBK_T2 or sFT5_BIT_SEL_IN; -- AA3D7 AA3E7
CMD_STT_Set <= CK_P_BIT and FAK;
CMD_STT_Set <= CK_P_BIT and FAK_T2; -- ?? FMD has FAK not FAK_T2
RST_CMD_RSTT_ADDR_OUT <= (FAK and T1) or RECYCLE_RST; -- AA3E6 AA3E2
CMD_STT_FL: entity FLL port map (S=>CMD_STT_Set, R=>RST_CMD_RSTT_ADDR_OUT, Q=>CMD_STT); -- AA3D7 AA3E7
sFT3_BIT_MPX_SHARE_REQ <= (ROS_SCAN or not CMD_STT) and (N1050_REQ_IN or sTAGS_IN.REQ_IN or (ALU_CHK_LCH and CHK_SW_PROC_SW) or sTAGS_IN.OPL_IN); -- AA3F2 AA3E5 AA3G4
@ -155,50 +158,72 @@ sTAGS_IN.SEL_IN <= TAGS_IN.SEL_IN or (DIAG_SW and BUS_O_REG(0)); -- AA3B4
sTAGS_IN.REQ_IN <= TAGS_IN.REQ_IN;
sTAGS_IN.MTR_IN <= TAGS_IN.MTR_IN;
MPX_BUS_OUT_BITS <= BUS_O_REG;
FAK_T2 <= FAK and (T2 and not ANY_PRIORITY_LCH); -- AA3B7 AA3F4 AA3E6
SetAdrO2 <= T3 and sADDR_OUT;
ADDR_O_2: entity FLL port map (S=>SetAdrO2, R=>RST_CMD_RSTT_ADDR_OUT, Q=>ADDR_OUT_2); -- AA3E4
SetAdrO1 <= FAK_T2 and CK_SALS_PWR(1);
ADDR_O_1: entity FLL port map (S=>SetAdrO1, R=>RST_CMD_RSTT_ADDR_OUT, Q=>sADDR_OUT); -- AA3D7 AA3E7
ADDR_OUT_2_FL: entity FLL port map (S=>SetAdrO2, R=>RST_CMD_RSTT_ADDR_OUT, Q=>ADDR_OUT_2); -- AA3E4
SetAdrOut <= FAK_T2 and CK_SALS_PWR(1);
ADDR_OUT_FL: entity FLL port map (S=>SetAdrOut, R=>RST_CMD_RSTT_ADDR_OUT, Q=>sADDR_OUT); -- AA3D7 AA3E7
ADDR_OUT <= sADDR_OUT;
SetCmdO <= FAK_T2 and CK_SALS_PWR(2);
RstCmdO <= not sTAGS_IN.ADR_IN and not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN;
CMD_O: entity FLL port map (S=>SetCmdO, R=>RstCmdO, Q=>CMD_OUT); -- AA3E4 AA3E5
TAGS_OUT.CMD_OUT <= CMD_OUT;
sTAGS_OUT.CMD_OUT <= CMD_OUT;
SetSrvO <= FAK_T2 and CK_SALS_PWR(3);
RstSrvO <= not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN;
SRV_O: entity FLL port map (S=>SetSrvO, R=>RstSrvO, Q=>SERV_OUT); -- AA3C7
SetCUBusyInlk <= sTAGS_IN.STA_IN and ADDR_OUT_2 and FBK_T2;
ResetCUBusyInlk <= not sADDR_OUT and T2;
CU_BUSY_INLK: entity FLL port map (S=>SetCUBusyInlk, R=>ResetCUBusyInlk, Q=>CUBusy); -- AA3B5
RST_STT_SEL_OUT <= not OP_OUT_SIG or CUBusy; -- AA3F7
ResetBusOCtrl <= not sADDR_OUT and not CMD_OUT and not SERV_OUT; -- AA3D7
BUS_O_CTRL: entity FLL port map (S=>SET_BUS_O_CTRL_LCH, R=>ResetBusOCtrl, Q=>BUSOCtrl); -- AA3J5
SetStartSelO <= sADDR_OUT and T2 and BUSOCtrl; -- AA3E6
ResetStartSelO <= RST_STT_SEL_OUT or (not N1401_MODE and sTAGS_IN.ADR_IN) or (not sADDR_OUT and Reset_SelO); -- AA3F5 AA3K3
SetStartSelO <= ADDR_OUT_2 and T2 and BUSOCtrl; -- AA3E6
ResetStartSelO <= RST_STT_SEL_OUT or (not N1401_MODE and sTAGS_IN.ADR_IN) or (not ADDR_OUT_2 and Reset_SelO); -- AA3F5 AA3K3
START_SEL_O: entity FLL port map (S=>SetStartSelO, R=>ResetStartSelO, Q=>StartSelO); -- AA3L4 AA3E7
sSEL_O_FT6 <= not CUBusy and (StartSelO or NO_1050_SEL_O or N1050_SEL_O); -- AA3E5
sSEL_O_FT6 <= not CUBusy and (StartSelO or NO_1050_SEL_O or sN1050_SEL_OUT); -- AA3E5
SEL_O_FT6 <= sSEL_O_FT6;
NO_1050_SEL_O <= not N1050_INSTALLED and sN1050_SEL_OUT; -- AA3D2
NO_1050_SEL_O <= not N1050_INSTALLED and n1050_SEL_O; -- AA3D2
SetSelReq <= not SelOInlk and T2 and sFT3_BIT_MPX_SHARE_REQ;
ResetSelReq <= SelOInlk or not sFT3_BIT_MPX_SHARE_REQ;
SEL_REQ: entity FLL port map (S=>SetSelReq, R=>ResetSelReq, Q=>sN1050_SEL_OUT); -- AA3F4
N1050_SEL_OUT <= sN1050_SEL_OUT;
-- To Select Out Propagation in 10B
P_1050_SEL_OUT <= sN1050_SEL_OUT;
SetSelOInlk <= (sTAGS_IN.ADR_IN and sTAGS_IN.OPL_IN) or (N1050_OP_IN and not N1050_CE_MODE); -- AA3B7
SEL_O_INLK: entity FLL port map (S=>SetSelOInlk, R=>not sTAGS_IN.OPL_IN, Q=>SelOInlk); -- AA3C7
sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) or not LOAD_IND or SUPPR_CTRL_LCH; -- AA3C7 AA3E5
-- sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) or not LOAD_IND or SUPPR_CTRL_LCH; -- AA3C7 AA3E5
sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) and not LOAD_IND and SUPPR_CTRL_LCH; -- AA3C7 AA3E5 ?? AA3C7 shown as 'OR'
SUPPR_O <= sSUPPR_O;
SS_RECYCLE_RST <= RECYCLE_RST; -- AA3G3 Single Shot ??
sOP_OUT <= OP_OUT_SIGNAL and not SS_RECYCLE_RST; -- AA3D6
TAGS_OUT.ADR_OUT2 <= ADDR_OUT_2;
TAGS_OUT.ADR_OUT <= sADDR_OUT;
TAGS_OUT.CMD_OUT <= CMD_OUT;
TAGS_OUT.SRV_OUT <= SERV_OUT;
TAGS_OUT.SEL_OUT <= sSEL_O_FT6; -- ??
TAGS_OUT.MTR_OUT <= METERING_OUT;
TAGS_OUT.CLK_OUT <= CLOCK_OUT;
TAGS_OUT.SUP_OUT <= sSUPPR_O;
TAGS_OUT.OPL_OUT <= sOP_OUT;
-- TAGS_OUT.SEL_OUT <= '0'; -- ??
TAGS_OUT.STA_OUT <= '0'; -- ??
TAGS_OUT.HLD_OUT <= '0'; -- ??
sTAGS_OUT.ADR_OUT2 <= ADDR_OUT_2;
sTAGS_OUT.ADR_OUT <= sADDR_OUT;
-- sTAGS_OUT.CMD_OUT <= CMD_OUT;
sTAGS_OUT.SRV_OUT <= SERV_OUT;
sTAGS_OUT.SEL_OUT <= sSEL_O_FT6; -- ??
sTAGS_OUT.MTR_OUT <= METERING_OUT;
sTAGS_OUT.CLK_OUT <= CLOCK_OUT;
sTAGS_OUT.SUP_OUT <= sSUPPR_O;
sTAGS_OUT.OPL_OUT <= sOP_OUT;
-- sTAGS_OUT.SEL_OUT <= '0'; -- ??
sTAGS_OUT.STA_OUT <= '0'; -- ??
sTAGS_OUT.HLD_OUT <= '0'; -- ??
TAGS_OUT <= sTAGS_OUT;
FI <= MPX_BUS_IN_BITS;
-- Output tag indicators not really shown
SELECT_OUT <= sSEL_O_FT6;

197
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@ -0,0 +1,197 @@
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-09C.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console input and output translation circuitry and
-- Control Character detection
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY n1050_TRANSLATE IS
port
(
-- Inputs
DATA_REG_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 10C
RDR_ON_LCH : IN STD_LOGIC; -- 10BD3
PUNCH_1_CLUTCH_1050 : IN STD_LOGIC; -- 10DD5 aka PCH_1_CLUTCH_1050
HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3
CLOCK_STT_RST : IN STD_LOGIC; -- 10AC2
RST_ATTACH : IN STD_LOGIC; -- 10BC2
W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX
n1050_RST : IN STD_LOGIC; -- 10BA3
ALLOW_STROBE : IN STD_LOGIC; -- 10CB6
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6
CE_RUN_MODE : IN STD_LOGIC; -- 10DB2
CE_TI_DECODE : IN STD_LOGIC; -- 10DB2
SET_LOWER_CASE : IN STD_LOGIC; -- 10CC5
n1050_RST_LCH : IN STD_LOGIC; -- 10BA3
READY_SHARE : IN STD_LOGIC; -- 10CE6
-- Outputs
TT2_POS_END : OUT STD_LOGIC; -- 10BD3
XLATE_UC : OUT STD_LOGIC; -- 10C
RD_SHARE_REQ_LCH : OUT STD_LOGIC; -- 10CD4 10BC3 10BD4
READ_SHARE_REQ : OUT STD_LOGIC; -- 10BD3
WRITE_UC : OUT STD_LOGIC; -- 10DD2
SET_SHIFT_LCH : OUT STD_LOGIC; -- 10CC4
PCH_1_HOME : OUT STD_LOGIC; -- 10DC5
RUN : OUT STD_LOGIC; -- 10BB3 10CC3 10BD1 10CE4 10CD2
UNGATED_RUN : OUT STD_LOGIC; -- 10BC4
READ : OUT STD_LOGIC; -- 10CD4
READ_INQ : OUT STD_LOGIC; -- 10CD4
LC_CHARACTER, UC_CHARACTER : OUT STD_LOGIC; -- 10CC5
WRITE_LCH : OUT STD_LOGIC; -- 10BD3 10AC1 10AA2 10BB1 10CA5 10CC3
WRITE_MODE : OUT STD_LOGIC; -- 10CD4
WRITE_STROBE : OUT STD_LOGIC; -- 10DC5
WRITE_LCH_RST : OUT STD_LOGIC; -- 10BA1
RD_OR_RD_INQ : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS
-- Clocks
-- T1,T2,T3,T4 : IN STD_LOGIC;
-- P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_TRANSLATE;
ARCHITECTURE FMD OF n1050_TRANSLATE IS
signal sLC_CHARACTER, sUC_CHARACTER : STD_LOGIC;
signal DataReg4511, DataReg23not00 : STD_LOGIC;
signal EndCode : STD_LOGIC;
signal DataRegSpecial1, DataRegSpecial2, DataRegSpecial3, DataRegSpecial : STD_LOGIC;
signal XLATE_UC_SET, XLATE_UC_RESET : STD_LOGIC;
signal RD_SHARE_REQ_SET, RD_SHARE_REQ_RESET : STD_LOGIC;
signal PREFIX_SET,PREFIX_RESET,PREFIX : STD_LOGIC;
signal BLOCK_SHIFT_SET,BLOCK_SHIFT : STD_LOGIC;
signal sWRITE_LCH : STD_LOGIC;
signal UPPER_CASE_DECODE, LOWER_CASE_DECODE : STD_LOGIC;
signal sRD_SHARE_REQ_LCH : STD_LOGIC;
signal sREAD, sREAD_INQ, sRD_OR_RD_INQ : STD_LOGIC;
signal DataReg01xxxxxx, DataRegLCA, DataRegLCB, DataRegLCC, DataRegLCD, DataRegLCE : STD_LOGIC;
signal DataRegLC, DataRegUC : STD_LOGIC;
signal PRT_IN_UC_SET, PRT_IN_UC_RESET, PRT_IN_UC : STD_LOGIC;
signal WRITE_SET, WRITE_RESET : STD_LOGIC;
signal sUNGATED_RUN : STD_LOGIC;
BEGIN
-- Fig 5-09C
-- Incoming character handling (keyboard codes AB8421 = 234567)
DataReg4511 <= DATA_REG_BUS(4) and DATA_REG_BUS(5); -- AC3F4 AC3D4 XX11XX
DataReg23not00 <= DATA_REG_BUS(2) or DATA_REG_BUS(3); -- AC3B6 01XXXX 10XXXX 11XXXX
-- EndCode <= DATA_REG_BUS(1) and DataReg4511 and not DATA_REG_BUS(2) and DATA_REG_BUS(6); -- 10x111x = EOB
EndCode <= '1' when DATA_REG_BUS="0000100" else '0'; -- End is 04=Ctrl+D
TT2_POS_END <= (EndCode and sRD_SHARE_REQ_LCH) or READY_SHARE; -- AC3F7 AC3F2 AC3C7 ?? *or* READY_SHARE ??
-- UPPER_CASE_DECODE <= not DATA_REG_BUS(7) and DATA_REG_BUS(6) and DataReg4511 and not DataReg23not00; -- AC3E2 AB8421=001110=Upshift
UPPER_CASE_DECODE <= '0';
-- LOWER_CASE_DECODE <= DATA_REG_BUS(6) and not DATA_REG_BUS(7) and DATA_REG_BUS(2) and DATA_REG_BUS(3) and DataReg4511; -- AC3F7 AB8421=111110=Downshift
LOWER_CASE_DECODE <= '0';
-- The following three lines are probably wrong
DataRegSpecial1 <= DataReg23not00 and DataReg4511 and DATA_REG_BUS(6) and DATA_REG_BUS(7); -- AC3E2 "xx1111" but not "111111"
DataRegSpecial2 <= DataReg4511 and DATA_REG_BUS(7) and not DataReg23not00 and not DATA_REG_BUS(6); -- AC3E2 "101101" = Return
DataRegSpecial3 <= DataReg4511 and not DATA_REG_BUS(6) and not DATA_REG_BUS(7); -- AC3B6 "xx1100"
-- DataRegSpecial <= DataRegSpecial1 or DataRegSpecial2 or DataRegSpecial3;
DataRegSpecial <= '0'; -- Ignore for now
XLATE_UC_SET <= UPPER_CASE_DECODE and X_TIME; -- AC3F2
XLATE_UC_RESET <= SET_LOWER_CASE or (X_TIME and LOWER_CASE_DECODE); -- AC3F2
XLATE_UC_FL: FLL port map (S=>XLATE_UC_SET, R=>XLATE_UC_RESET, Q=>XLATE_UC); -- ?????
RD_SHARE_REQ_SET <= not DataRegSpecial and not UPPER_CASE_DECODE and not LOWER_CASE_DECODE and sRD_OR_RD_INQ and Y_TIME;
RD_SHARE_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH or (CE_RUN_MODE and CE_TI_DECODE);
RD_SHARE_REQ_FL: FLL port map(S=>RD_SHARE_REQ_SET, R=>RD_SHARE_REQ_RESET, Q=>sRD_SHARE_REQ_LCH); -- AC3F5 AC3C7
RD_SHARE_REQ_LCH <= sRD_SHARE_REQ_LCH;
READ_SHARE_REQ <= sRD_SHARE_REQ_LCH and not Y_TIME; -- AC3E3
sREAD <= HOME_RDR_STT_LCH and RDR_ON_LCH and not sWRITE_LCH; -- AC2G7
READ <= sREAD;
sREAD_INQ <= not sWRITE_LCH and RDR_ON_LCH and PROCEED_LCH; -- AC2G7
READ_INQ <= sREAD_INQ;
sRD_OR_RD_INQ <= sREAD or sREAD_INQ;
RD_OR_RD_INQ <= sRD_OR_RD_INQ;
PCH_1_HOME <= PUNCH_1_CLUTCH_1050 or sREAD or sREAD_INQ; -- AC2G3
-- Outgoing character handling
-- Prefix is 0x100111 i.e. 27 or 67
PREFIX_SET <= not DATA_REG_BUS(0) and DATA_REG_BUS(2) and not DATA_REG_BUS(3)
and not DATA_REG_BUS(4) and DATA_REG_BUS(5) and DATA_REG_BUS(6) and DATA_REG_BUS(7) and Z_TIME; -- AC3B7 AC3F2 AC3D6
PREFIX_FL: FLL port map(S=>PREFIX_SET,R=>Y_TIME,Q=>PREFIX); -- AC3F2 AC3G5
-- Block Shift prevents the shift mechanism from being triggered
BLOCK_SHIFT_SET <= PREFIX and X_TIME;
BLOCK_SHIFT_FL: FLL port map(S=>BLOCK_SHIFT_SET,R=>W_TIME,Q=>BLOCK_SHIFT); -- AC3F2 AC3C6
DataReg01xxxxxx <= not DATA_REG_BUS(0) and DATA_REG_BUS(1); -- AC3D5 AC3B4
DataRegLCA <= not DATA_REG_BUS(5) and DATA_REG_BUS(7) and DataReg01xxxxxx; -- 01xxx0x1 = 01xx0001 "/" 01xx0011 01xx1001 01xx1011 ".$,#"
DataRegLCB <= not DATA_REG_BUS(4) and not DATA_REG_BUS(6) and DataReg01xxxxxx; -- 01xx0x0x = 01xx0000 "-&" 01xx0001 "/" 01xx0100 01xx0101
DataRegLCC <= DATA_REG_BUS(0) and DATA_REG_BUS(1) and DATA_REG_BUS(2) and DATA_REG_BUS(3); -- AC3F5 1111xxxx = 0-9 = LC
DataRegLCD <= DATA_REG_BUS(2) and DATA_REG_BUS(3) and not DATA_REG_BUS(6) and not DATA_REG_BUS(7)
and DataReg01xxxxxx; -- AC3B7 0111xx00 = 01110000 01110100 01111000 01111100 "@"
DataRegLCE <= DATA_REG_BUS(0) and not DATA_REG_BUS(1); -- AC3E5 10xxxxxx = LC
DataRegLC <= DataRegLCA or DataRegLCB or DataRegLCC or DataRegLCD or DataRegLCE;
DataRegUC <= not DataRegLC and DATA_REG_BUS(1);
sLC_CHARACTER <= DataRegLC and not BLOCK_SHIFT;
LC_CHARACTER <= sLC_CHARACTER;
sUC_CHARACTER <= DataRegUC and not BLOCK_SHIFT;
UC_CHARACTER <= sUC_CHARACTER;
-- PRT_IN_UC remembers whether the printer is already in UC mode
PRT_IN_UC_SET <= sUC_CHARACTER and Z_TIME and ALLOW_STROBE;
PRT_IN_UC_RESET <= (sLC_CHARACTER and Z_TIME and ALLOW_STROBE) or SET_LOWER_CASE; -- AC3F4
PRINT_IN_UC_FL: FLL port map(S=>PRT_IN_UC_SET,R=>PRT_IN_UC_RESET,Q=>PRT_IN_UC); -- ?????
WRITE_UC <= PRT_IN_UC;
-- For now the SHIFT function is disabled as it is not required for ASCII output
-- SET_SHIFT_LCH <= not ((PRT_IN_UC and sLC_CHARACTER and sWRITE_LCH) or (sUC_CHARACTER and sWRITE_LCH and not PRT_IN_UC)); -- AC2E5 AC3D4
SET_SHIFT_LCH <= '0';
WRITE_SET <= not RDR_ON_LCH and not PUNCH_1_CLUTCH_1050 and HOME_RDR_STT_LCH; -- AC2G7
WRITE_RESET <= CLOCK_STT_RST or RST_ATTACH;
WRITE_FL : FLL port map(S=>WRITE_SET,R=>WRITE_RESET,Q=>sWRITE_LCH); -- AC2J5 AC2H6
WRITE_LCH <= sWRITE_LCH;
WRITE_LCH_RST <= sWRITE_LCH;
WRITE_MODE <= WRITE_SET and not n1050_RST; -- AC2D7
WRITE_STROBE <= Z_TIME and ALLOW_STROBE and sWRITE_LCH; -- AC2K6
-- Stuff common to input and output
sUNGATED_RUN <= sREAD_INQ or sREAD or sWRITE_LCH; -- AC2G3
UNGATED_RUN <= sUNGATED_RUN;
RUN <= sUNGATED_RUN and not n1050_RST_LCH; -- AC2K5 AC2H6
END FMD;

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---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10A.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console clock control and generation
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
Library UNISIM;
use UNISIM.vcomponents.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY n1050_CLOCK IS
port
(
-- Inputs
WRITE_LCH : IN STD_LOGIC; -- 09CD2
READ_OR_READ_INQ : IN STD_LOGIC; -- 09CC5
RST_ATTACH : IN STD_LOGIC; -- 10BC2
PUNCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
READ_CLK_INTLK_LCH : IN STD_LOGIC; -- 10BA2
RDR_1_CLUTCH : IN STD_LOGIC; -- 10DD5
CRLF : IN STD_LOGIC; -- ?
-- Outputs
CLOCK_1 : OUT STD_LOGIC; -- 10CD1 10CA4
W_TIME, X_TIME, Y_TIME, Z_TIME : OUT STD_LOGIC;
CLK_STT_RST : OUT STD_LOGIC; -- 09CE1
-- Temp
-- POSTRIG, NEGTRIG : OUT STD_LOGIC;
-- OSCOut,C1,C2 : OUT STD_LOGIC;
-- OSCOut,C1,C2 : OUT STD_LOGIC;
-- Clocks
clk : IN STD_LOGIC -- 50MHz clock
);
END n1050_CLOCK;
ARCHITECTURE FMD OF n1050_CLOCK IS
-- Output rate is 9600bps or 960chars/sec or 1.04ms/char. We set the clock to run at 1.2ms/4 or 300us (300 * 50 = 15000 cycles)
-- constant ClockDivider : integer := 15000;
constant ClockDivider : integer := 250; -- Gives 5us OSC rate
signal OSC : STD_LOGIC; -- Inverted signal
signal CLK_START : STD_LOGIC;
signal TRIGER : STD_LOGIC;
signal nTRIG : STD_LOGIC;
signal BIN_CNTR : STD_LOGIC_VECTOR(1 to 2);
signal Counter : integer;
signal sCLK_STT_RST : STD_LOGIC;
signal CLK_START_SET, CLK_START_RESET : STD_LOGIC;
signal W_SET, X_SET, Y_SET, Z_SET : STD_LOGIC;
signal W_RESET, X_RESET, Y_RESET, Z_RESET : STD_LOGIC;
signal sW_TIME, sX_TIME, sY_TIME, sZ_TIME : STD_LOGIC;
BEGIN
-- Fig 5-10A
sCLK_STT_RST <= OSC and not BIN_CNTR(1) and sZ_TIME and not sW_TIME; -- AC2H4
CLK_STT_RST <= sCLK_STT_RST;
CLK_START_SET <= (PUNCH_1_CLUTCH and not READ_CLK_INTLK_LCH and READ_OR_READ_INQ)
or (RDR_1_CLUTCH and WRITE_LCH and not CRLF);
CLK_START_RESET <= RST_ATTACH or sCLK_STT_RST;
CLK_START_FL : FLL port map(CLK_START_SET,CLK_START_RESET,CLK_START); -- AC2G6 AC2F6
BIN_CNTR_P: process(OSC,RST_ATTACH) is
begin
if RST_ATTACH='1' then
BIN_CNTR <= "01";
else if rising_edge(OSC) then
BIN_CNTR <= BIN_CNTR + "01";
end if;
end if;
end process;
OSC_P : process(CLK_START,clk) is
begin
if falling_edge(clk) then
if (CLK_START='0') then
OSC <= '1';
Counter <= 0;
else
Counter <= Counter + 1;
if Counter=ClockDivider then
Counter <= 0;
end if;
if (Counter > (ClockDivider/2)) then
OSC <= '1';
else
OSC <= '0';
end if;
end if;
end if;
end process;
TRIGER <= (not BIN_CNTR(1) and WRITE_LCH) or (READ_OR_READ_INQ and BIN_CNTR(2)); -- AC2G7
nTRIG <= (not BIN_CNTR(2) and not WRITE_LCH) or (BIN_CNTR(1) and WRITE_LCH); -- AC2F7 AC2M2
-- POSTRIG <= TRIGER;
-- NEGTRIG <= nTRIG;
-- OSCOut <= OSC;
-- C1 <= BIN_CNTR(1);
-- C2 <= BIN_CNTR(2);
W_SET <= not sY_TIME and sZ_TIME and (TRIGER and CLK_START); -- AC2E7 AC2F6 ?? 'not' gate ignored
X_SET <= not sZ_TIME and sW_TIME and nTRIG;
Y_SET <= not sW_TIME and sX_TIME and TRIGER; -- AC2G2
Z_SET <= (not sX_TIME and sY_TIME and nTRIG) or RST_ATTACH or (OSC and not CLK_START); -- AC2E7 ?? RST_ATTACH or (OSC and not CLK_START) ??
W_RESET <= (sX_TIME and TRIGER) or RST_ATTACH; -- AC2D7
X_RESET <= (sY_TIME and nTRIG) or RST_ATTACH; -- AC2G3
Y_RESET <= (sZ_TIME and TRIGER) or RST_ATTACH or (OSC and not CLK_START); -- AC2F7
Z_RESET <= (sW_TIME and nTRIG); -- AC2G3
W_JK: FDRSE port map(C=>clk,Q=>sW_TIME,R=>W_RESET,S=>W_SET,CE=>'0',D=>'0');
-- W_FL : FLL port map(W_SET,W_RESET,sW_TIME); -- AC2G2
W_TIME <= sW_TIME;
X_JK: FDRSE port map(C=>clk,Q=>sX_TIME,R=>X_RESET,S=>X_SET,CE=>'0',D=>'0');
-- X_FL : FLL port map(X_SET,X_RESET,sX_TIME); -- AC2G2
X_TIME <= sX_TIME;
Y_JK: FDRSE port map(C=>clk,Q=>sY_TIME,R=>Y_RESET,S=>Y_SET,CE=>'0',D=>'0');
-- Y_FL : FLL port map(Y_SET,Y_RESET,sY_TIME); -- AC2G2
Y_TIME <= sY_TIME;
Z_JK: FDRSE port map(C=>clk,Q=>sZ_TIME,R=>Z_RESET,S=>Z_SET,CE=>'0',D=>'0');
-- Z_FL : FLL port map(Z_SET,Z_RESET,sZ_TIME); -- AC2F5
Z_TIME <= sZ_TIME;
CLOCK1_FL : FLL port map(W_SET,X_RESET,CLOCK_1); -- ?? CLOCK_1 isn't defined in the diagrams
-- This is a guess at CLOCK_1 being W_TIME OR X_TIME, but can't do that directly without possible glitches
END FMD;

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---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10B.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console tag signal generation
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY n1050_TAGS IS
port
(
-- Inputs
RD_OR_RD_INQ : IN STD_LOGIC; -- 09CC5
Y_TIME : IN STD_LOGIC; -- 10AXX
RD_INLK_RST : IN STD_LOGIC; -- 10DC5
WRITE_LCH_RST : IN STD_LOGIC; -- 09CE2
PCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
TT2_POS_END : IN STD_LOGIC; -- 09CB5
WRITE_LCH : IN STD_LOGIC; -- 09CD2
Z_TIME : IN STD_LOGIC; -- 10AXX
CE_DATA_ENTER_GT : IN STD_LOGIC; -- 10DA2
CE_TA_DECODE : IN STD_LOGIC; -- 10DA1
GT_1050_TAGS_OUT : IN STD_LOGIC; -- 10CE2
RECYCLE_RESET : IN STD_LOGIC; -- 04CA5
-- CE_MODE : IN STD_LOGIC; -- ---A6
CE_RESET : IN STD_LOGIC; -- 10DC2
RUN : IN STD_LOGIC; -- 09CE6
TT3_POS_1050_OPER : IN STD_LOGIC; -- 10DD4
TAGS_OUT_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 10CD1
n1050_CE_MODE : IN STD_LOGIC; -- 10DB3
P_1050_SEL_IN : IN STD_LOGIC; -- 08DC1
P_1050_SEL_OUT : IN STD_LOGIC; -- 08DD6
MPX_OPN_LCH_GT : IN STD_LOGIC; -- 08CE3
CK_SAL_P_BIT : IN STD_LOGIC; -- 01CXX
EXIT_MPLX_SHARE : IN STD_LOGIC; -- 10DB3
ADDR_OUT : IN STD_LOGIC; -- 08DA5
RD_SHARE_REQ : IN STD_LOGIC; -- 09CC6
RD_SHARE_REQ_LCH : IN STD_LOGIC; -- 09CC6
SUPPRESS_OUT : IN STD_LOGIC; -- 08DD6
WR_SHARE_REQ : IN STD_LOGIC; -- 10CA6
CE_SEL_O : IN STD_LOGIC; -- 10DB2
INTRV_REQ : IN STD_LOGIC; -- 10CD6
RDY_SHARE : IN STD_LOGIC; -- 10CE6
UNGATED_RUN : IN STD_LOGIC; -- 09CE6
REQUEST_KEY : IN STD_LOGIC; -- 10DE5
-- Outputs
n1050_RST_LCH : OUT STD_LOGIC; -- 10DF2 09CD1 10CA5 09CE5
HOME_RDR_START_LCH : OUT STD_LOGIC; -- 09CE4 09CE1 10DE2
HOME_RDR_STOP : OUT STD_LOGIC; -- 10DC5
PROCEED_LCH : OUT STD_LOGIC; -- 09CE4 10CC2 10DE2
MICRO_SHARE_LCH : OUT STD_LOGIC; -- 10DE2
RDR_ON_LCH : OUT STD_LOGIC; -- 09CE4 10DE2 09CE1
TA_REG_POS_4 : OUT STD_LOGIC; -- 10DE2
AUDIBLE_ALARM : OUT STD_LOGIC; -- 14AXX
CR_LF : OUT STD_LOGIC; -- 10AC1 10DE2
TA_REG_POS_6_ATTENTION_RST : OUT STD_LOGIC; -- ---D4 10DE2 10CE5
CPU_LINES_TO_1050 : OUT CONN_1050; -- 10DE3
SHARE_REQ_RST : OUT STD_LOGIC; -- 09CC5 10CE4 10CA5
T_REQUEST : OUT STD_LOGIC; -- 07BD3 06BA3 07BB3
CPU_REQUEST_IN : OUT STD_LOGIC; -- 10DE3
n1050_OP_IN : OUT STD_LOGIC; -- 08DD4 10CA4
n1050_REQ_IN : OUT STD_LOGIC; -- 08DD2
TT6_POS_ATTN : OUT STD_LOGIC; -- 10DC4 04AB6
n1050_INSTALLED : OUT STD_LOGIC; -- 08DC1
n1050_SEL_O : OUT STD_LOGIC; -- 08DD5
TA_REG_SET : OUT STD_LOGIC; -- 10CB4
RD_CLK_INLK_LCH : OUT STD_LOGIC; -- 10AC1
RESTORE : OUT STD_LOGIC; -- 10CD4
RST_ATTACH : OUT STD_LOGIC; -- 09C 10A 10C
DEBUG : INOUT DEBUG_BUS;
-- Clocks
clk : IN STD_LOGIC;
Clock1ms : IN STD_LOGIC;
Clock60Hz : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_TAGS;
ARCHITECTURE FMD OF n1050_TAGS IS
signal RD_CLK_INLK_SET, sRD_CLK_INLK_LCH : STD_LOGIC;
signal n1050_RST_RESET, n1050_RST_SET, s1050_RST_LCH : STD_LOGIC;
signal sRST_ATTACH : STD_LOGIC;
signal sTA_REG_SET, TA_REG_RST : STD_LOGIC;
signal SET_HOME_RDR_STT : STD_LOGIC;
signal sHOME_RDR_START_LCH : STD_LOGIC;
signal SET_PROCEED : STD_LOGIC;
signal sPROCEED_LCH : STD_LOGIC;
signal MICRO_SHARE_REQ : STD_LOGIC;
signal SET_MICRO_SHARE : STD_LOGIC;
signal sMICRO_SHARE_LCH : STD_LOGIC;
signal SET_RDR_2 : STD_LOGIC;
signal sRDR_ON_LCH : STD_LOGIC;
signal MS5000_IN : STD_LOGIC;
signal sTA_REG_POS_4 : STD_LOGIC;
signal MS1000_IN : STD_LOGIC;
signal sCR_LF : STD_LOGIC;
signal sTA_REG_POS_6_ATTENTION_RST : STD_LOGIC;
signal n1050_SEL_OUT : STD_LOGIC;
signal n1050_SEL_IN : STD_LOGIC;
signal SEL_O_DLY : STD_LOGIC;
signal SET_SEL_O_DET, RESET_SEL_O_DET : STD_LOGIC;
signal SEL_O_DET : STD_LOGIC;
signal SET_1050_OP_IN, RESET_1050_OP_IN : STD_LOGIC;
signal sn1050_OP_IN : STD_LOGIC;
signal SET_SEL_O_DLY, RESET_SEL_O_DLY : STD_LOGIC;
signal MPX_LCH_OFF : STD_LOGIC;
signal CPU_SEL_O_OR_SEL_IN : STD_LOGIC;
signal SET_1050_EXIT_SHARE_REQ : STD_LOGIC;
signal n1050_EXIT_SHARE_REQ : STD_LOGIC;
signal sCPU_REQUEST_IN : STD_LOGIC;
signal SET_PREPARE_TO_SHARE, RESET_PREPARE_TO_SHARE : STD_LOGIC;
signal PREPARE_TO_SHARE : STD_LOGIC;
signal SET_ATTN_INTLK, RESET_ATTN_INTLK : STD_LOGIC;
signal ATTN_INTLK : STD_LOGIC := '1';
signal SS20_IN, SS20 : STD_LOGIC;
signal SET_ATTN,RESET_ATTN : STD_LOGIC;
signal sTT6_POS_ATTN : STD_LOGIC := '0';
signal sRESTORE : STD_LOGIC;
BEGIN
-- Fig 5-10B
RD_CLK_INLK_SET <= RD_OR_RD_INQ and Y_TIME; -- AC3E3
RD_CLK_INLK: FLL port map(RD_CLK_INLK_SET,RD_INLK_RST,sRD_CLK_INLK_LCH); -- AC3E3, AC3F2
RD_CLK_INLK_LCH <= sRD_CLK_INLK_LCH;
n1050_RST_RESET <= not sRD_CLK_INLK_LCH and not WRITE_LCH_RST; -- AC2J5
n1050_RST_SET <= TAGS_OUT_BUS(7) and sTA_REG_SET; -- AC2K5
n1050_RST : FLL port map(n1050_RST_SET, n1050_RST_RESET, s1050_RST_LCH); -- AC2K5 AC2E2
n1050_RST_LCH <= s1050_RST_LCH;
CPU_LINES_TO_1050.n1050_RST_LCH <= s1050_RST_LCH;
CPU_LINES_TO_1050.n1050_RESET <= ((((sRD_CLK_INLK_LCH and not PCH_1_CLUTCH) or (WRITE_LCH and Z_TIME)) and s1050_RST_LCH) or sRST_ATTACH) and TT3_POS_1050_OPER; -- AC2H4 AC2G3 AC2K3 AC2K6
sTA_REG_SET <= (CE_DATA_ENTER_GT and CE_TA_DECODE) or (P3 and GT_1050_TAGS_OUT); -- AC2K3
TA_REG_SET <= sTA_REG_SET;
TA_REG_RST <= (CE_DATA_ENTER_GT and CE_TA_DECODE) or (T3 and GT_1050_TAGS_OUT) or sRST_ATTACH; -- AC2J2
sRST_ATTACH <= (RECYCLE_RESET and not n1050_CE_MODE) or CE_RESET; -- AC2H3 AC2H5 AC2K2
RST_ATTACH <= sRST_ATTACH;
MS16: SS port map(Clock1ms,16,RUN,sRESTORE); -- 16ms Single-shot AC2L2
CPU_LINES_TO_1050.RESTORE <= sRESTORE;
RESTORE <= sRESTORE;
SET_HOME_RDR_STT <= TAGS_OUT_BUS(0) and sTA_REG_SET;
HOME_RDR_STT_FL: FLL port map(SET_HOME_RDR_STT,TA_REG_RST,sHOME_RDR_START_LCH); -- AC2H3 AC2K4
HOME_RDR_START_LCH <= sHOME_RDR_START_LCH;
CPU_LINES_TO_1050.HOME_RDR_START <= sHOME_RDR_START_LCH and TT3_POS_1050_OPER and not sPROCEED_LCH; -- AC2L6
HOME_RDR_STOP <= TT3_POS_1050_OPER and not RUN; -- AC2K6
SET_PROCEED <= TAGS_OUT_BUS(3) and sTA_REG_SET;
PROCEED_FL: FLL port map(SET_PROCEED,TA_REG_RST,sPROCEED_LCH); -- AC2D6 AC2K7
PROCEED_LCH <= sPROCEED_LCH;
CPU_LINES_TO_1050.PROCEED <= sPROCEED_LCH and not RD_SHARE_REQ_LCH and not MICRO_SHARE_REQ; -- AC2K6
MICRO_SHARE_REQ <= (not SUPPRESS_OUT and sMICRO_SHARE_LCH) or (sPROCEED_LCH and sMICRO_SHARE_LCH); -- AC2K7
SET_MICRO_SHARE <= TAGS_OUT_BUS(2) and sTA_REG_SET;
MICRO_SHARE_FL: FLL port map(SET_MICRO_SHARE,TA_REG_RST,sMICRO_SHARE_LCH); -- AC2H3 AC2K4
MICRO_SHARE_LCH <= sMICRO_SHARE_LCH;
SET_RDR_2 <= TAGS_OUT_BUS(1) and sTA_REG_SET;
RDR_2_FL: FLL port map(SET_RDR_2,TA_REG_RST,sRDR_ON_LCH); -- AC2H3 AC2K4
RDR_ON_LCH <= sRDR_ON_LCH;
CPU_LINES_TO_1050.RDR_2_HOLD <= ((sRDR_ON_LCH or not RD_SHARE_REQ) and TT3_POS_1050_OPER) -- AC2J5 AC2K6
or (sRDR_ON_LCH and TT2_POS_END) or not WRITE_LCH; -- AC2L6 AC2H4
MS5000_IN <= sTA_REG_SET and TAGS_OUT_BUS(4);
MS5000: SS port map(Clock60Hz,300,MS5000_IN, sTA_REG_POS_4); -- AC2G3 AC3G6 AC3F2 5s single-shot
TA_REG_POS_4 <= sTA_REG_POS_4;
AUDIBLE_ALARM <= sTA_REG_POS_4; -- AC3H5
MS1000_IN <= (sRST_ATTACH and TT3_POS_1050_OPER) or (sTA_REG_SET and TAGS_OUT_BUS(5)); -- AC2K7
MS1000: SS port map(clk,5000000,MS1000_IN, sCR_LF); -- AC2L2 AC2D6 1s single-shot : 100ms (5000000) is enough
CR_LF <= sCR_LF;
CPU_LINES_TO_1050.CARR_RETURN_AND_LINE_FEED <= sCR_LF; -- AC2L6
sTA_REG_POS_6_ATTENTION_RST <= sTA_REG_SET and TAGS_OUT_BUS(6); -- AC2H4
TA_REG_POS_6_ATTENTION_RST <= sTA_REG_POS_6_ATTENTION_RST;
n1050_SEL_OUT <= not P_1050_SEL_IN or (n1050_CE_MODE and not sn1050_OP_IN) or (CPU_SEL_O_OR_SEL_IN and SEL_O_DLY); -- AC3E7 AC3D7
n1050_SEL_IN <= not P_1050_SEL_OUT or (n1050_CE_MODE and not sn1050_OP_IN) or (CPU_SEL_O_OR_SEL_IN and SEL_O_DLY); -- AC3D7 AC3E7
SET_SEL_O_DET <= T1 and CPU_SEL_O_OR_SEL_IN;
RESET_SEL_O_DET <= not CPU_SEL_O_OR_SEL_IN or sRST_ATTACH;
SEL_O_DET_FL: FLL port map(SET_SEL_O_DET,RESET_SEL_O_DET,SEL_O_DET); -- AC3E6
SET_SEL_O_DLY <= T3 and SEL_O_DET and not sn1050_OP_IN;
RESET_SEL_O_DLY <= sRST_ATTACH or not CPU_SEL_O_OR_SEL_IN;
SEL_O_DLY_FL: FLL port map(SET_SEL_O_DLY,RESET_SEL_O_DLY,SEL_O_DLY); -- AC3E6
SET_1050_OP_IN <= (CPU_SEL_O_OR_SEL_IN and PREPARE_TO_SHARE) or (n1050_CE_MODE and PREPARE_TO_SHARE);
RESET_1050_OP_IN <= MPX_LCH_OFF or sRST_ATTACH; -- ??
n1050_OP_IN_FL: FLL port map(SET_1050_OP_IN,RESET_1050_OP_IN,sn1050_OP_IN);
n1050_OP_IN <= sn1050_OP_IN;
SET_1050_EXIT_SHARE_REQ <= MPX_OPN_LCH_GT and not CK_SAL_P_BIT; -- AC3C7
n1050_EXIT_SHARE_REQ_FL : FLL port map(SET_1050_EXIT_SHARE_REQ,T1,n1050_EXIT_SHARE_REQ); -- AC3C6 AC3E4
SHARE_REQ_RST <= (n1050_EXIT_SHARE_REQ and not n1050_CE_MODE and T4) or EXIT_MPLX_SHARE; -- AC3E4
MPX_LCH_OFF <= EXIT_MPLX_SHARE or (n1050_EXIT_SHARE_REQ and not n1050_CE_MODE and T4); -- AC3E4
T_REQUEST <= not n1050_CE_MODE and sCPU_REQUEST_IN; -- AC3D6 ?? Not sure about sCPU_REQUEST_IN - diagram is missing this!
CPU_SEL_O_OR_SEL_IN <= n1050_SEL_OUT or n1050_SEL_IN; -- AC3D7 AC3E7 AC3B6
sCPU_REQUEST_IN <= MICRO_SHARE_REQ or RD_SHARE_REQ_LCH or WR_SHARE_REQ or INTRV_REQ or RDY_SHARE
or (not sMICRO_SHARE_LCH and UNGATED_RUN and sTT6_POS_ATTN); -- AC3F7 AC3D6
CPU_REQUEST_IN <= sCPU_REQUEST_IN;
SET_PREPARE_TO_SHARE <= (not CPU_SEL_O_OR_SEL_IN and n1050_CE_MODE and not ADDR_OUT and sCPU_REQUEST_IN) or (sCPU_REQUEST_IN and CE_SEL_O); -- AC3C7 AC3E2
RESET_PREPARE_TO_SHARE <= not sCPU_REQUEST_IN or sRST_ATTACH;
PREPARE_TO_SHARE_FL: FLL port map(SET_PREPARE_TO_SHARE,RESET_PREPARE_TO_SHARE,PREPARE_TO_SHARE); -- AC3E6
n1050_REQ_IN <= sCPU_REQUEST_IN and not n1050_CE_MODE;
RESET_ATTN <= sTA_REG_POS_6_ATTENTION_RST or sRST_ATTACH; -- AC3B7 AC3B4
SS20_IN <= TT3_POS_1050_OPER and REQUEST_KEY; -- AC3D6
SS20_SS: SS port map(Clock1ms,20,SS20_IN,SS20); -- 20ms single-shot AC3G6
SET_ATTN_INTLK <= RESET_ATTN or sTT6_POS_ATTN;
RESET_ATTN_INTLK <= SS20 and REQUEST_KEY; -- AC3B6 AC3C7 - Typo, AC3C7 should be N?
ATTN_INTLK_FL: FLL port map(SET_ATTN_INTLK,RESET_ATTN_INTLK,ATTN_INTLK); -- AC3C6 AC3D6 - ?? Not sure about this
SET_ATTN <= ATTN_INTLK and RESET_ATTN_INTLK;
-- ATTN_FL: FLL port map(SET_ATTN,RESET_ATTN,sTT6_POS_ATTN); -- AC3C6 AC3C7
sTT6_POS_ATTN <= '0'; -- ?? Temporarily disable 1050 REQ function
TT6_POS_ATTN <= sTT6_POS_ATTN;
n1050_INSTALLED <= '1'; -- AC3D7, AC3E7
n1050_SEL_O <= n1050_SEL_OUT; -- Propagate SELECT OUT untouched
with DEBUG.Selection select
DEBUG.Probe <=
sCPU_REQUEST_IN when 0,
MICRO_SHARE_REQ when 1,
RD_SHARE_REQ_LCH when 2,
WR_SHARE_REQ when 3,
INTRV_REQ when 4,
RDY_SHARE when 5,
sMICRO_SHARE_LCH when 6,
UNGATED_RUN when 7,
RD_OR_RD_INQ when 8,
sRD_CLK_INLK_LCH when 9,
WRITE_LCH when 10,
TT2_POS_END WHEN 11,
sCR_LF when 12,
Z_TIME when 13,
sRDR_ON_LCH when 14,
sPROCEED_LCH when 15,
'1' when others;
END FMD;

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---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10C.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console data latches and gating
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY n1050_DATA IS
port
(
-- Inputs
E_SW_SEL_BUS : IN E_SW_BUS_Type; -- 04CE1
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03DA3
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02BA3
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02AE6
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05CA2
XLATE_UC : IN STD_LOGIC; -- 09C
WR_LCH : IN STD_LOGIC; -- 09CD2 aka WRITE_LCH
RUN : IN STD_LOGIC; -- 09CE6
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
-- TT4_POS_HOME_STT : IN STD_LOGIC; -- 10DD5
RD_OR_RD_INQ : IN STD_LOGIC; -- 09CC5
W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08BE3
CLOCK_1 : IN STD_LOGIC; -- 10AA5
PCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
GT_1050_BUS_OUT, GT_1050_TAGS_OUT : IN STD_LOGIC; -- 04CE6
n1050_OP_IN : IN STD_LOGIC; -- 10BC5
SET_SHIFT_LCH : IN STD_LOGIC; -- 09CD6
TA_REG_SET : IN STD_LOGIC; -- 10BB2
RST_ATTACH : IN STD_LOGIC; -- 10BC2
n1050_OPER : IN STD_LOGIC; -- 10DE4
READ_INQ : IN STD_LOGIC; -- 09CE6
RD_SHARE_REQ_LCH : IN STD_LOGIC; -- 09CC6
READ : IN STD_LOGIC; -- 09CE6
WRITE_MODE : IN STD_LOGIC; -- 09CFD2
RESTORE : IN STD_LOGIC; -- 10BD2
OUTPUT_SEL_AND_READY : IN STD_LOGIC; -- 10DD4
SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6
n1050_RST_LCH : IN STD_LOGIC; -- 10BA3
RDR_1_CLUTCH : IN STD_LOGIC; -- 10DD5
UC_CHARACTER, LC_CHARACTER : IN STD_LOGIC; -- 09CD2
-- Z_BUS_0, Z_BUS_3 : IN STD_LOGIC; -- 06BDX
-- TT3_POS_1050_OPER : IN STD_LOGIC; -- 10DD4
TA_REG_POS_6_ATTN_RST : IN STD_LOGIC; -- 10BE3
PCH_BITS : IN STD_LOGIC_VECTOR(0 to 6);
-- CE controls
CE_GT_TA_OR_TE : IN STD_LOGIC;
CE_DATA_ENTER_GT : IN STD_LOGIC;
CE_TE_DECODE : IN STD_LOGIC;
CE_RUN_MODE : IN STD_LOGIC; -- 10DB3
n1050_CE_MODE : IN STD_LOGIC;
CE_BITS : IN STD_LOGIC_VECTOR(0 to 7); -- 10DA1
-- Outputs
A_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 07CA6
DATA_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 09C
TAGS_OUT : OUT STD_LOGIC_VECTOR(0 to 7); -- 10BB1 11AA2
NPL_BITS : OUT STD_LOGIC_VECTOR(0 to 7);
PTT_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- Output to printer ("RDR")
TE_LCH : OUT STD_LOGIC;
WR_SHARE_REQ : OUT STD_LOGIC; -- 10BD5
ALLOW_STROBE : OUT STD_LOGIC; -- 09CD4 09CE1
GT_WRITE_REG : OUT STD_LOGIC; -- 10DB4
FORCE_SHIFT_CHAR : OUT STD_LOGIC; -- 10DB4
FORCE_LC_SHIFT : OUT STD_LOGIC; -- 10DB4
SET_LOWER_CASE : OUT STD_LOGIC; -- 09CD4 09CB5
n1050_INTRV_REQ : OUT STD_LOGIC; -- 10BD4 04AA4
READY_SHARE : OUT STD_LOGIC; -- 10BD4 09CB4
TT5_POS_INTRV_REQ : OUT STD_LOGIC; -- 10DC4
-- Buses
TT_BUS: INOUT STD_LOGIC_VECTOR(0 to 7);
GTD_TT3: OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_DATA;
ARCHITECTURE FMD OF n1050_DATA IS
type ConversionAtoE is array(0 to 255) of STD_LOGIC_VECTOR(0 to 7);
signal ASCII_TO_EBCDIC : ConversionAtoE :=
(
character'Pos(cr) => "00010101",
character'Pos(lf) => "00100101",
character'Pos(' ') => "01000000",
character'Pos('.') => "01001011",
character'Pos('<') => "01001100",
character'Pos('(') => "01001101",
character'Pos('+') => "01001110",
character'Pos('&') => "01010000",
character'Pos('$') => "01011011",
character'Pos(')') => "01011101",
character'Pos(';') => "01011110",
character'Pos('-') => "01100000",
character'Pos('/') => "01100001",
character'Pos(',') => "01101011",
character'Pos('%') => "01101100",
character'Pos('>') => "01101110",
character'Pos('?') => "01101111",
character'Pos(':') => "01111010",
character'Pos('#') => "01111011",
character'Pos('@') => "01111100",
character'Pos('0') => "11110000", character'Pos('1') => "11110001", character'Pos('2') => "11110010",
character'Pos('3') => "11110011", character'Pos('4') => "11110100",
character'Pos('5') => "11110101", character'Pos('6') => "11110110", character'Pos('7') => "11110111",
character'Pos('8') => "11111000", character'Pos('9') => "11111001",
character'Pos('A') => "11000001", character'Pos('B') => "11000010", character'Pos('C') => "11000011",
character'Pos('D') => "11000100", character'Pos('E') => "11000101", character'Pos('F') => "11000110",
character'Pos('G') => "11000111", character'Pos('H') => "11001000", character'Pos('I') => "11001010",
character'Pos('J') => "11010001", character'Pos('K') => "11010010", character'Pos('L') => "11010011",
character'Pos('M') => "11010100", character'Pos('N') => "11010101", character'Pos('O') => "11010110",
character'Pos('P') => "11010111", character'Pos('Q') => "11011000", character'Pos('R') => "11011001",
character'Pos('S') => "11100010", character'Pos('T') => "11100011", character'Pos('U') => "11100100",
character'Pos('V') => "11100101", character'Pos('W') => "11100110", character'Pos('X') => "11100111",
character'Pos('Y') => "11101000", character'Pos('Z') => "11101001",
character'Pos('a') => "10000001", character'Pos('b') => "10000010", character'Pos('c') => "10000011",
character'Pos('d') => "10000100", character'Pos('e') => "10000101", character'Pos('f') => "10000110",
character'Pos('g') => "10000111", character'Pos('h') => "10001000", character'Pos('i') => "10001010",
character'Pos('j') => "10010001", character'Pos('k') => "10010010", character'Pos('l') => "10010011",
character'Pos('m') => "10010100", character'Pos('n') => "10010101", character'Pos('o') => "10010110",
character'Pos('p') => "10010111", character'Pos('q') => "10011000", character'Pos('r') => "10011001",
character'Pos('s') => "10100010", character'Pos('t') => "10100011", character'Pos('u') => "10100100",
character'Pos('v') => "10100101", character'Pos('w') => "10100110", character'Pos('x') => "10100111",
character'Pos('y') => "10101000", character'Pos('z') => "10101001",
others => "01101111");
type ConversionEtoA is array(0 to 255) of character;
signal EBCDIC_TO_ASCII : ConversionEtoA :=
(
2#00010101# => cr,
2#00100101# => lf,
2#01000000# => ' ',
2#01001011# => '.',
2#01001100# => '<',
2#01001101# => '(',
2#01001110# => '+',
2#01001111# => '|',
2#01010000# => '&',
2#01011010# => '!',
2#01011011# => '$',
2#01011100# => '*',
2#01011101# => ')',
2#01011110# => ';',
2#01011111# => '~',
2#01100000# => '-',
2#01100001# => '/',
2#01101011# => ',',
2#01101100# => '%',
2#01101101# => '_',
2#01101110# => '>',
2#01101111# => '?',
2#01111010# => ':',
2#01111011# => '#',
2#01111100# => '@',
2#01111101# => ''',
2#01111110# => '=',
2#01111111# => '"',
2#11110000# => '0', 2#11110001# => '1', 2#11110010# => '2', 2#11110011# => '3', 2#11110100# => '4',
2#11110101# => '5', 2#11110110# => '6', 2#11110111# => '7', 2#11111000# => '8', 2#11111001# => '9',
2#11000001# => 'A', 2#11000010# => 'B', 2#11000011# => 'C', 2#11000100# => 'D', 2#11000101# => 'E',
2#11000110# => 'F', 2#11000111# => 'G', 2#11001000# => 'H', 2#11001001# => 'I',
2#11010001# => 'J', 2#11010010# => 'K', 2#11010011# => 'L', 2#11010100# => 'M', 2#11010101# => 'N',
2#11010110# => 'O', 2#11010111# => 'P', 2#11011000# => 'Q', 2#11011001# => 'R',
2#11100010# => 'S', 2#11100011# => 'T', 2#11100100# => 'U', 2#11100101# => 'V', 2#11100110# => 'W',
2#11100111# => 'X', 2#11101000# => 'Y', 2#11101001# => 'Z',
2#10000001# => 'a', 2#10000010# => 'b', 2#10000011# => 'c', 2#10000100# => 'd', 2#10000101# => 'e',
2#10000110# => 'f', 2#10000111# => 'g', 2#10001000# => 'h', 2#10001001# => 'i',
2#10010001# => 'j', 2#10010010# => 'k', 2#10010011# => 'l', 2#10010100# => 'm', 2#10010101# => 'n',
2#10010110# => 'o', 2#10010111# => 'p', 2#10011000# => 'q', 2#10011001# => 'r',
2#10100010# => 's', 2#10100011# => 't', 2#10100100# => 'u', 2#10100101# => 'v', 2#10100110# => 'w',
2#10100111# => 'x', 2#10101000# => 'y', 2#10101001# => 'z',
others => '?');
signal sGT_1050_BUS_OUT, sGT_1050_TAGS_OUT : STD_LOGIC;
signal sSET_LOWER_CASE : STD_LOGIC;
signal sTE_LCH : STD_LOGIC;
signal sSET_LOW_CASE : STD_LOGIC;
signal sDATA_REG : STD_LOGIC_VECTOR(0 to 7);
signal sNPL_BITS : STD_LOGIC_VECTOR(0 to 7);
signal GT_1050_BUS_TO_A, GT_1050_TAGS_TO_A : STD_LOGIC;
signal sTAGS_OUT : STD_LOGIC_VECTOR(0 to 7);
signal DATA_REG_LATCH : STD_LOGIC;
signal DATA_REG_IN : STD_LOGIC_VECTOR(0 to 7);
signal TI_P_BIT : STD_LOGIC;
signal sPTT_BITS : STD_LOGIC_VECTOR(0 to 6);
signal sGTD_TT3 : STD_LOGIC;
signal CE_TE_LCH_SET : STD_LOGIC;
signal TE_LCH_SET, TE_LCH_RESET : STD_LOGIC;
signal sGT_WRITE_REG : STD_LOGIC;
signal WR_SHARE_REQ_SET, WR_SHARE_REQ_RESET,sWR_SHARE_REQ : STD_LOGIC;
signal ALLOW_STROBE_SET, ALLOW_STROBE_RESET, sALLOW_STROBE : STD_LOGIC;
signal SHIFT_SET, SHIFT_RESET : STD_LOGIC;
signal sSHIFT : STD_LOGIC := '0';
signal INTRV_REQ_SET, INTRV_REQ_RESET, sINTRV_REQ : STD_LOGIC;
signal n1050_INTRV_REQ_RESET : STD_LOGIC;
signal NOT_OPER_RESET : STD_LOGIC;
signal NOT_OPER : STD_LOGIC := '0';
signal RDY_SHARE_SET, RDY_SHARE_RESET, sRDY_SHARE : STD_LOGIC;
signal CancelCode : STD_LOGIC;
BEGIN
-- Fig 5-10C
GT_1050_BUS_TO_A <= (E_SW_SEL_BUS.TI_SEL and USE_MANUAL_DECODER) or
(USE_ALT_CA_DECODER and not GTD_CA_BITS(0) and GTD_CA_BITS(1) and GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AB3C7 AA=1 CA=0111
GT_1050_TAGS_TO_A <= (E_SW_SEL_BUS.TT_SEL and USE_MANUAL_DECODER) or
(USE_BASIC_CA_DECO and not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AA2C6 AA=0 CA=0001
A_REG_BUS <= not(((sNPL_BITS & TI_P_BIT) and (0 to 8=>GT_1050_BUS_TO_A)) or ((TT_BUS & '0') and (0 to 8=>GT_1050_TAGS_TO_A))); -- AC2E2 - Note: Inverted
DATA_REG_PH: PHV8 port map(D=>DATA_REG_IN,L=>DATA_REG_LATCH,Q=>sDATA_REG); -- AC3B2
DATA_REG_BUS <= sDATA_REG;
DATA_REG_LATCH <= (CE_DATA_ENTER_GT and CE_TE_DECODE) or (RD_OR_RD_INQ and W_TIME) or (T3 and sGT_1050_BUS_OUT) or not RUN; -- AC3P5
TAGS_OUT <= DATA_REG_IN; -- ?
sGT_1050_BUS_OUT <= GT_1050_BUS_OUT; -- AC2D6
sGT_1050_TAGS_OUT <= GT_1050_TAGS_OUT; -- AC2M4
DATA_REG_IN <= (Z_BUS(0 to 7) and (0 to 7=>(sGT_1050_BUS_OUT or sGT_1050_TAGS_OUT)))
or (CE_BITS and (0 to 7=>CE_GT_TA_OR_TE))
or (('0' & PCH_BITS) and (0 to 7=>(CLOCK_1 and PCH_1_CLUTCH))); -- AC2B4 AC2H6 AC2M6 AC2M2
sGTD_TT3 <= TT_BUS(3) and n1050_CE_MODE; -- AC2H5 AC2L4
GTD_TT3 <= sGTD_TT3;
TT_BUS(7) <= EVENPARITY(sDATA_REG(1 to 7)) and WR_LCH and RUN and not TT_BUS(0); -- AC2E4 AC2J2
-- CancelCode <= '1' when sDATA_REG(1 to 7)="1100000" else '0'; -- DATA_REG=X1100000
CancelCode <= '1' when sDATA_REG(1 to 7)="0010101" else '0'; -- DATA_REG (ASCII) = 15 = ^U
TT_BUS(0) <= CancelCode and PROCEED_LCH and TT_BUS(4); -- AL2F5 AC2D6
-- The following converts the card code CBA8421 on the DATA_REG bus to EBCDIC
-- C P P P P
-- B 0 0 1 1
-- A 0 1 0 1
-- =====================
-- 0 =40 @=7C -=60 &=50
-- 1 1=F1 /=61 j=91 a=81
-- 2 2=F2 s=A2 k=92 b=82
-- 3 3=F3 t=A3 l=93 c=83
-- 4 4=F4 u=A4 m=94 d=84
-- 5 5=F5 v=A5 n=95 e=85
-- 6 6=F6 w=A6 o=96 f=86
-- 7 7=F7 x=A7 p=97 g=87
-- 8 8=F8 y=A8 q=98 h=88
-- 9 9=F9 z=A9 r=99 i=89
-- A 0=FA CAN
-- B #=7B ,=6B $=5B .=4B
-- C
-- D CR
-- E UC EOB LC
-- F
-- For the purposes of this project, this will convert ASCII on CBA8421 into EBCDIC in MPL
-- sNPL_BITS(0) <= 0; -- AC3J2
-- sNPL_BITS(1) <= 0; -- AC3J2
-- sNPL_BITS(2) <= 0; -- AC3K2
-- sNPL_BITS(3) <= 0; -- AC3H2
-- sNPL_BITS(4) <= 0; -- AC3H2
-- sNPL_BITS(5) <= 0; -- AC3K2
-- sNPL_BITS(6) <= 0; -- AC3J2
-- sNPL_BITS(7) <= 0; -- AC3J2
sNPL_BITS <= ASCII_TO_EBCDIC(Conv_Integer(sDATA_REG));
-- sNPL_BITS <= STD_LOGIC_VECTOR(to_unsigned(Conv_Integer(sDATA_REG),8)); -- * * Temporary debug - no translation
NPL_BITS <= sNPL_BITS;
TI_P_BIT <= EVENPARITY(sNPL_BITS(0 to 7)); -- AC2G4
-- The following converts EBCDIC on the DATA_REG bus to card code CBA8421
-- For the purposes of this project, this will convert EBCDIC in DATA_REG into ASCII in PTT
-- sPTT_BIT_C <= EVEN_PARITY(...); -- C AC3G4
-- sPTT_BIT_B <= 0; -- AC3H2
-- sPTT_BIT_A <= 0; -- AC3K2
-- sPTT_BIT_8 <= 0; -- AC3G2
-- sPTT_BIT_4 <= 0; -- AC3G2
-- sPTT_BIT_2 <= 0; -- AC3G2
-- sPTT_BIT_1 <= 0; -- AC3G2
sPTT_BITS <= STD_LOGIC_VECTOR(to_unsigned(Character'Pos(EBCDIC_TO_ASCII(Conv_Integer(sDATA_REG))),7));
PTT_BITS <= sPTT_BITS;
CE_TE_LCH_SET <= (CE_DATA_ENTER_GT and CE_TE_DECODE) and n1050_OP_IN and CLOCK_1; -- AC2D7 AC2L6 ?? Ignore NOT in AC2M4
TE_LCH_SET <= CE_TE_LCH_SET or (CE_RUN_MODE and CE_TE_DECODE) or (sGT_1050_BUS_OUT and T4); -- AC2J7
sGT_WRITE_REG <= (Z_TIME and sALLOW_STROBE and not sSHIFT); -- AC2C6
GT_WRITE_REG <= sGT_WRITE_REG; -- AC2M4 AC2H6
TE_LCH_RESET <= sSET_LOWER_CASE or sGT_WRITE_REG;
TE_LCH_FL: FLL port map(S=>TE_LCH_SET,R=>TE_LCH_RESET,Q=>sTE_LCH); -- AC2B6
TE_LCH <= sTE_LCH;
WR_SHARE_REQ_SET <= not n1050_RST_LCH and W_TIME and WR_LCH and not sTE_LCH;
WR_SHARE_REQ_RESET <= RST_ATTACH or SHARE_REQ_RST;
WR_SHARE_REQ_FL: FLL port map(S=>WR_SHARE_REQ_SET,R=>WR_SHARE_REQ_RESET,Q=>sWR_SHARE_REQ); -- AC2K5 AC2D6
WR_SHARE_REQ <= sWR_SHARE_REQ;
ALLOW_STROBE_SET <= RDR_1_CLUTCH and Y_TIME and sTE_LCH;
ALLOW_STROBE_RESET <= sSET_LOWER_CASE or (Y_TIME and not RDR_1_CLUTCH) or X_TIME;
ALLOW_STROBE_FL: FLL port map(S=>ALLOW_STROBE_SET,R=>ALLOW_STROBE_RESET,Q=>sALLOW_STROBE); -- AC2B6
ALLOW_STROBE <= sALLOW_STROBE;
SHIFT_SET <= (n1050_CE_MODE and SET_SHIFT_LCH) or (SET_SHIFT_LCH and sTE_LCH and Y_TIME);
SHIFT_RESET <= X_TIME or sSET_LOWER_CASE;
SHIFT_FL: FLL port map(S=>SHIFT_SET,R=>SHIFT_RESET,Q=>sSHIFT); -- AC2B6
FORCE_SHIFT_CHAR <= (UC_CHARACTER and Z_TIME and sSHIFT) or (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2C6
FORCE_LC_SHIFT <= (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2D6 ?? not?
sSET_LOWER_CASE <= TA_REG_SET or RST_ATTACH; -- AC2C6 AC2D6
SET_LOWER_CASE <= sSET_LOWER_CASE;
INTRV_REQ_SET <= (not n1050_OPER and READ_INQ and not RD_SHARE_REQ_LCH)
or (not RD_SHARE_REQ_LCH and READ and (not TT_BUS(1) or not TT_BUS(3))) -- AC2G6 AC2H5
or ( WRITE_MODE
and not RESTORE
and not Z_TIME
and not TA_REG_SET
and (not TT_BUS(3) or not OUTPUT_SEL_AND_READY)
and (not CE_DATA_ENTER_GT or not n1050_CE_MODE)); -- AC2E5 AC2K7
INTRV_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH; -- AC2H5 AC2H3
INTRV_REQ_FL: FLL port map(S=>INTRV_REQ_SET,R=>INTRV_REQ_RESET,Q=>sINTRV_REQ); -- AC2G6 AC2H3
TT5_POS_INTRV_REQ <= sINTRV_REQ;
n1050_INTRV_REQ_RESET <= n1050_CE_MODE or (Z_BUS(0) and GT_1050_TAGS_OUT) or (GT_1050_TAGS_OUT and Z_BUS(3)) or RST_ATTACH or sRDY_SHARE;
n1050_INTRV_REQ_FL: FLL port map(S=>sINTRV_REQ,R=>n1050_INTRV_REQ_RESET,Q=>n1050_INTRV_REQ); -- AC2K3 AC2H4
NOT_OPER_RESET <= RUN or sRDY_SHARE;
NOT_OPER_FL: FLL port map(S=>not n1050_OPER,R=>NOT_OPER_RESET,Q=>NOT_OPER); -- AC2G5 ?? Set input inverted
RDY_SHARE_SET <= not sINTRV_REQ and TT_BUS(3) and NOT_OPER; -- AC2J7
RDY_SHARE_RESET <= INTRV_REQ_RESET or RUN or TA_REG_POS_6_ATTN_RST;
RDY_SHARE_FL: FLL port map(S=>RDY_SHARE_SET,R=>RDY_SHARE_RESET,Q=>sRDY_SHARE); -- AC2F6 AC2E5
READY_SHARE <= sRDY_SHARE;
with DEBUG.Selection select
DEBUG.Probe <=
sDATA_REG(0) when 0,
sDATA_REG(1) when 1,
sDATA_REG(2) when 2,
sDATA_REG(3) when 3,
sDATA_REG(4) when 4,
sDATA_REG(5) when 5,
sDATA_REG(6) when 6,
sDATA_REG(7) when 7,
sNPL_BITS(0) when 8,
sNPL_BITS(1) when 9,
sNPL_BITS(2) when 10,
sNPL_BITS(3) when 11,
sNPL_BITS(4) when 12,
sNPL_BITS(5) when 13,
sNPL_BITS(6) when 14,
sNPL_BITS(7) when 15;
END FMD;

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---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10D.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console attachment and CE section
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY n1050_ATTACH IS
port
(
-- Inputs
-- CE Cable
CE_CABLE_IN : IN CE_IN := ("00000000",'0','0','0','0','0','0','0','0','0','0');
-- CE DATA BUS From 1050 DATA section
PTT_BITS : IN STD_LOGIC_VECTOR(0 to 6);
DATA_REG : IN STD_LOGIC_VECTOR(0 to 7);
NPL_BITS : IN STD_LOGIC_VECTOR(0 to 7);
-- Other stuff
TE_LCH : IN STD_LOGIC; -- 10CB5
WRITE_UC : IN STD_LOGIC; -- 09CD6
XLATE_UC : IN STD_LOGIC; -- 09CB6
CPU_REQUEST_IN : IN STD_LOGIC; -- 10BD6
n1050_OP_IN : IN STD_LOGIC; -- 10BB5
HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3
RDR_ON_LCH : IN STD_LOGIC; -- 10BD3
MICRO_SHARE_LCH : IN STD_LOGIC; -- 10BC3
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
TA_REG_POS_4 : IN STD_LOGIC; -- 10BE3
CR_LF : IN STD_LOGIC; -- 10BE3
TA_REG_POS_6 : IN STD_LOGIC; -- 10BE3
n1050_RST : IN STD_LOGIC; -- 10BE2
GT_WR_REG : IN STD_LOGIC; -- 10CB6
FORCE_LC_SHIFT : IN STD_LOGIC; -- 10CC6
FORCE_SHIFT_CHAR : IN STD_LOGIC; -- 10CC6
WR_STROBE : IN STD_LOGIC; -- 09CD2
PCH_1_HOME : IN STD_LOGIC; -- 09CD6
HOME_RDR_STOP : IN STD_LOGIC; -- 10BB3
TT2_POS_END : IN STD_LOGIC; -- 09CB5 - NOT IN FMD
TT5_POS_INTRV_REQ : IN STD_LOGIC; -- 10CD5
TT6_POS_ATTN : IN STD_LOGIC; -- 10BD6
CPU_LINES_ENTRY : IN CONN_1050; -- 10BE3
-- Outputs
-- CE Cable
CE_CABLE_OUT : OUT CE_OUT;
-- CE DATA BUS to 10C (1050 DATA)
CE_GT_TA_OR_TE : OUT STD_LOGIC; -- 10C
CE_DATA_ENTER_GT : OUT STD_LOGIC; -- 10BB1 10CA4 10C
CE_TE_DECODE : OUT STD_LOGIC; -- 10CA4 10C
CE_MODE_AND_TE_LCH : OUT STD_LOGIC;
n1050_CE_MODE : OUT STD_LOGIC; -- 10CB3 10BD5
-- Other stuff
CE_SEL_OUT : OUT STD_LOGIC; -- 10BD5
CE_TI_DECODE : OUT STD_LOGIC; -- 09CC5
CE_RUN_MODE : OUT STD_LOGIC; -- 09CC5
CE_TA_DECODE : OUT STD_LOGIC; -- 10BB1
CE_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 10C
EXIT_MPLX_SHARE : OUT STD_LOGIC; -- 10BB5
CE_DATA_ENTER_NC : OUT STD_LOGIC;
-- TT3_POS_1050_OPER : OUT STD_LOGIC; -- 10BE2 10BB2 10BE2 10CE5 Moved to TT_BUS(3)
-- TT4_POS_HOME_STT : OUT STD_LOGIC; -- 10CD2 Moved to TT_BUS(4)
OUTPUT_SEL_AND_RDY : OUT STD_LOGIC; -- 10CD4
n1050_OPER : OUT STD_LOGIC; -- 10CC4 10CE4
PUNCH_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- 10CE1
READ_INTLK_RST : OUT STD_LOGIC; -- 10BA1
PUNCH_1_CLUTCH : OUT STD_LOGIC; -- 10CE1 10AC1
-- PCH_1_CLUTCH_1050 : OUT STD_LOGIC; -- 09CE1 10BA1 09CD5
REQUEST_KEY : OUT STD_LOGIC; -- 10BE4
RDR_1_CLUTCH : OUT STD_LOGIC;
-- In/Out TT bus
TT_BUS : INOUT STD_LOGIC_VECTOR(0 to 7);
GTD_TT3 : IN STD_LOGIC;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END n1050_ATTACH;
ARCHITECTURE FMD OF n1050_ATTACH IS
signal sCE_TA_DECODE, sCE_TE_DECODE : STD_LOGIC;
signal sCE_DATA_ENTER_GT : STD_LOGIC;
signal sn1050_CE_MODE : STD_LOGIC;
signal sPUNCH_1_CLUTCH : STD_LOGIC;
signal sRDR_1_CLUTCH : STD_LOGIC;
signal sOUTPUT_SEL_AND_RDY : STD_LOGIC;
signal TT1_POS_RDR_2_RDY, sTT3_POS_1050_OPER, sTT4_POS_HOME_STT : STD_LOGIC;
signal PCH_CONN_ENTRY : PCH_CONN;
signal RDR_1_CONN_EXIT : RDR_CONN;
signal CPU_LINES_EXIT : CONN_1050;
BEGIN
-- Fig 5-10D
sCE_TA_DECODE <= CE_CABLE_IN.CE_TA_DECODE;
CE_TA_DECODE <= sCE_TA_DECODE;
CE_GT_TA_OR_TE <= (CE_CABLE_IN.CE_TA_DECODE and sCE_DATA_ENTER_GT) or (sCE_TE_DECODE and sCE_DATA_ENTER_GT); -- AC2G5
sCE_DATA_ENTER_GT <= CE_CABLE_IN.CE_TI_OR_TE_RUN_MODE;
CE_DATA_ENTER_GT <= sCE_DATA_ENTER_GT;
-- CE cable entry
CE_BUS <= CE_CABLE_IN.CE_BIT; -- AC2M3
sCE_TE_DECODE <= CE_CABLE_IN.CE_TE_DECODE; -- AC2M2
CE_TE_DECODE <= sCE_TE_DECODE;
CE_SEL_OUT <= CE_CABLE_IN.CE_SEL_OUT; -- AC2M2
CE_TI_DECODE <= CE_CABLE_IN.CE_TI_DECODE; -- AC2M2
CE_RUN_MODE <= not CE_CABLE_IN.CE_MODE; -- AC2M2
CE_MODE_AND_TE_LCH <= (TE_LCH and sn1050_CE_MODE) or CE_CABLE_IN.CE_SEL_OUT; -- AC2E7
sn1050_CE_MODE <= CE_CABLE_IN.CE_MODE;
n1050_CE_MODE <= sn1050_CE_MODE;
EXIT_MPLX_SHARE <= CE_CABLE_IN.CE_EXIT_MPLX_SHARE;
CE_DATA_ENTER_NC <= CE_CABLE_IN.CE_DATA_ENTER_NC;
-- CE cable exit
CE_CABLE_OUT.PTT_BITS <= PTT_BITS;
CE_CABLE_OUT.DATA_REG <= DATA_REG;
CE_CABLE_OUT.RDR_1_CLUTCH <= sRDR_1_CLUTCH;
CE_CABLE_OUT.WRITE_UC <= WRITE_UC;
CE_CABLE_OUT.XLATE_UC <= XLATE_UC;
CE_CABLE_OUT.PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
CE_CABLE_OUT.NPL <= NPL_BITS;
CE_CABLE_OUT.OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
CE_CABLE_OUT.TT <= TT_BUS(0 to 2) & GTD_TT3 & TT_BUS(4 to 7);
CE_CABLE_OUT.CPU_REQUEST_IN <= CPU_REQUEST_IN;
CE_CABLE_OUT.n1050_OP_IN <= n1050_OP_IN;
CE_CABLE_OUT.HOME_RDR_STT_LCH <= HOME_RDR_STT_LCH;
CE_CABLE_OUT.RDR_ON_LCH <= RDR_ON_LCH;
CE_CABLE_OUT.MICRO_SHARE_LCH <= MICRO_SHARE_LCH;
CE_CABLE_OUT.PROCEED_LCH <= PROCEED_LCH;
CE_CABLE_OUT.TA_REG_POS_4 <= TA_REG_POS_4;
CE_CABLE_OUT.CR_LF <= CR_LF;
CE_CABLE_OUT.TA_REG_POS_6 <= TA_REG_POS_6;
CE_CABLE_OUT.n1050_RST <= n1050_RST;
-- RDR connection (output)
-- FORCE_LC_SHIFT and FORCE_SHIFT_CHAR makes 0111110 (downshift)
-- FORCE_SHIFT_CHAR makes 0001110 (upshift)
-- We remove this in favour of simple ASCII on the output
-- RDR_1_CONN_EXIT.RDR_BITS <= (PTT_BITS(0) and GT_WR_REG) -- C
-- & ((PTT_BITS(1) and GT_WR_REG) or FORCE_LC_SHIFT) -- B
-- & ((PTT_BITS(2) and GT_WR_REG) or FORCE_LC_SHIFT) -- A
-- & ((PTT_BITS(3) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 8
-- & ((PTT_BITS(4) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 4
-- & ((PTT_BITS(5) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 2
-- & (PTT_BITS(6) and GT_WR_REG); -- 1
RDR_1_CONN_EXIT.RDR_BITS <= PTT_BITS;
RDR_1_CONN_EXIT.RD_STROBE <= WR_STROBE;
CPU_LINES_EXIT <= CPU_LINES_ENTRY;
-- TT Bus
TT_BUS(1) <= TT1_POS_RDR_2_RDY;
TT_BUS(2) <= TT2_POS_END;
TT_BUS(3) <= sTT3_POS_1050_OPER;
-- TT3_POS_1050_OPER <= sTT3_POS_1050_OPER;
TT_BUS(4) <= sTT4_POS_HOME_STT;
-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
TT_BUS(5) <= TT5_POS_INTRV_REQ;
TT_BUS(6) <= TT6_POS_ATTN;
-- PCH connections (input)
PUNCH_BITS <= PCH_CONN_ENTRY.PCH_BITS; -- AC2L4
READ_INTLK_RST <= '1' when PCH_CONN_ENTRY.PCH_BITS="0000000" else '0'; -- AC2E3
sPUNCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050; -- AC2M2 AC2J7
PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH;
-- PCH_1_CLUTCH_1050 <= sPUNCH_1_CLUTCH;
TT1_POS_RDR_2_RDY <= PCH_CONN_ENTRY.RDR_2_READY; -- AC2M5 AC2L5
sTT3_POS_1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- AC2J5
sTT4_POS_HOME_STT <= PCH_CONN_ENTRY.HOME_RDR_STT_LCH; -- AC2M5 AC2L5
-- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT;
sOUTPUT_SEL_AND_RDY <= PCH_CONN_ENTRY.HOME_OUTPUT_DEV_RDY;
OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY;
sRDR_1_CLUTCH <= PCH_CONN_ENTRY.RDR_1_CLUTCH_1050; -- AC2M4
RDR_1_CLUTCH <= sRDR_1_CLUTCH;
n1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- FA1D4
REQUEST_KEY <=PCH_CONN_ENTRY.REQ_KEY; -- FA1D4
console : entity ibm1050 port map(
SerialIn => PCH_CONN_ENTRY,
SerialOut => RDR_1_CONN_EXIT,
SerialControl => CPU_LINES_EXIT,
serialInput => serialInput,
serialOutput => serialOutput,
clk => clk);
END FMD;

23
FMD2030_UDC1.vhd
View File

@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -34,8 +34,8 @@
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Minor changes, and add DEBUG facility
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -239,7 +239,7 @@ port(
STG_MEM_SEL : OUT STD_LOGIC; -- to 08D
-- Debug
DEBUG : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
@ -393,6 +393,7 @@ wx_sect: entity WX_Regs (FMD) port map (
CROS_STROBE => CROS_STROBE,
CROS_GO_PULSE => CROS_GO_PULSE,
SALS => sSALS,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
@ -456,7 +457,9 @@ wx_sect: entity WX_Regs (FMD) port map (
SAL_PC => SAL_PC,
SET_IND_ROSAR => SET_IND_ROSAR,
GT_BU_ROSAR_TO_WX_REG => GT_BU_ROSAR_TO_WX_REG,
SET_FW => SET_FW
SET_FW => SET_FW,
DEBUG => DEBUG
);
-- CCROS microcode storage
@ -533,7 +536,7 @@ x6x7_sect: entity X6X7 (FMD) port map (
GT_UV_TO_WX_REG => GT_UV_TO_WX_REG,
DIAG_LATCH_RST => DIAG_LATCH_RST,
-- Debug
DEBUG => DEBUG,
DEBUG => open,
-- Clocks
T1 => T1,
@ -550,7 +553,7 @@ priority_sect: entity Priority (FMD) port map (
-- Inputs
RECYCLE_RST => sRECYCLE_RST,
S_REG_1_BIT => S(1),
SALS_CDREG => sSALS.SALS_CD,
SALS_CDREG => sCTRL.CTRL_CD,
MACH_RST_SW => sMACH_RST_SW,
DATA_READY_1 => DATA_READY_1,
DATA_READY_2 => DATA_READY_2,
@ -735,7 +738,7 @@ css_sect: entity ClockStartStop port map (
CLOCK_START => CLOCK_START,
EARLY_ROAR_STOP => EARLY_ROAR_STOP,
HARD_STOP_LCH => HARD_STOP_LCH,
-- DEBUG => DEBUG,
DEBUG => open,
-- Clocks
T2 => T2,
@ -1221,13 +1224,13 @@ RW1st32k: entity RWStgClk1st32k port map(
DATA_READY_1 => DATA_READY_1,
DATA_READY_2 => DATA_READY_2,
-- DEBUG => DEBUG,
DEBUG => open,
-- Clocks
T1 => T1,T2 => T2,T3 => T3,T4 => T4,
CLK => CLK
);
READ_ECHO_1 <= sREAD_ECHO_1;
READ_ECHO_2 <= sREAD_ECHO_2;
WRITE_ECHO_1 <= sWRITE_ECHO_1;

71
FMD2030_UDC2.vhd
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@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -34,8 +34,8 @@
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Add Mpx and 1050 buses, and Storage interface
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -60,6 +60,7 @@ port(
MN : OUT STD_LOGIC_VECTOR(0 to 15);
-- M_P, N_P : OUT STD_LOGIC;
E_BUS : IN E_SW_BUS_Type;
-- External MPX connections:
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
@ -90,6 +91,10 @@ port(
IND_MAIN_STG, IND_LOC_STG, IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG, IND_CHK_B_REG, IND_CHK_STOR_ADDR, IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS, IND_CHK_ROS_ADDR, IND_CHK_STOR_DATA, IND_CHK_ALU : OUT STD_LOGIC;
-- Hardware interface
StorageIn : IN STORAGE_IN_INTERFACE;
StorageOut : OUT STORAGE_OUT_INTERFACE;
-- Controls
CLOCK_START : IN STD_LOGIC;
@ -220,7 +225,7 @@ port(
EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : IN STD_LOGIC; -- 13A, 11A
-- Outputs to UDC3
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
-- Selector & Mpx channels
SX1_RD_CYCLE,SX2_RD_CYCLE,SX1_WR_CYCLE,SX2_WR_CYCLE : IN STD_LOGIC;
@ -228,10 +233,21 @@ port(
N_SEL_SHARE_HOLD : IN STD_LOGIC;
GK,HK : IN STD_LOGIC_VECTOR(0 to 3);
PROTECT_LOC_CPU_OR_MPX, PROTECT_LOC_SEL_CHNL : OUT STD_LOGIC;
FO : OUT STD_LOGIC_VECTOR(0 to 8);
FO, FI : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_OPN_LT_GATE : OUT STD_LOGIC;
ADDR_OUT : OUT STD_LOGIC;
MPX_BUS_IN_TO_CPU : OUT STD_LOGIC_VECTOR(0 to 8);
n1050_SEL_IN : OUT STD_LOGIC;
n1050_INSTALLED : IN STD_LOGIC;
n1050_REQ_IN : IN STD_LOGIC;
n1050_OP_IN : IN STD_LOGIC;
n1050_CE_MODE : IN STD_LOGIC;
n1050_SEL_O : IN STD_LOGIC;
P_1050_SEL_OUT : OUT STD_LOGIC;
P_1050_SEL_IN : OUT STD_LOGIC;
-- Debug
DEBUG : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Clocks
CLOCK_IN : IN STD_LOGIC;
@ -252,7 +268,7 @@ signal ADDR_IN : STD_LOGIC;
signal STATUS_IN : STD_LOGIC;
signal SERVICE_IN : STD_LOGIC;
signal SELECT_OUT : STD_LOGIC;
signal ADDR_OUT : STD_LOGIC;
signal sADDR_OUT : STD_LOGIC;
signal COMMAND_OUT : STD_LOGIC;
signal SERVICE_OUT : STD_LOGIC;
signal SUPPRESS_OUT : STD_LOGIC;
@ -298,7 +314,7 @@ signal sZ_BUS_LO_DIGIT_PARITY : STD_LOGIC;
signal sMN_PC : STD_LOGIC;
signal sPROTECT_LOC_CPU_OR_MPX : STD_LOGIC;
signal sXL,sXH,sXXH : STD_LOGIC;
signal SUPPR_CTRL_LCH,OP_OUT_SIG,MPX_OPN_LT_GATE,SX1_MASK,SX2_MASK,FAK,SET_BUS_O_CTRL_LCH : STD_LOGIC;
signal SUPPR_CTRL_LCH,OP_OUT_SIG,SX1_MASK,SX2_MASK,FAK,SET_BUS_O_CTRL_LCH : STD_LOGIC;
-- signal sMPX_BUS_O_REG : STD_LOGIC_VECTOR(0 to 8);
signal sFT2, sFT7 : STD_LOGIC;
@ -346,7 +362,7 @@ MpxInd_sect: entity MpxInd (FMD) port map (
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => ADDR_OUT,
ADDR_OUT => sADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT,
@ -518,7 +534,9 @@ r_reg: entity RREG_STG port map (
R_REG_BUS => sR,
P_8F_DETECTED => P_8F_DETECTED,
StorageIn => StorageIn,
StorageOut => StorageOut,
-- Clocks
T1 => sT1,
T2 => sT2,
@ -768,8 +786,8 @@ MpxReg1 : entity MpxFOFB port map (
XXH <= sXXH;
FO <= sFO & sFO_P;
FT7 <= sFT7;
MpxChnlCtrls: entity MpxFA port map (
MpxChnlCtrls: entity MpxFA port map ( -- 5-08D
BUS_O_REG(0 to 7) => sFO,
BUS_O_REG(8) => sFO_P,
DIAG_SW => DIAG_SW,
@ -780,7 +798,8 @@ MpxChnlCtrls: entity MpxFA port map (
TAGS_OUT => MPX_TAGS_O,
TAGS_IN => MPX_TAGS_I,
FAK => FAK,
FI => FI,
FAK => FAK,
RECYCLE_RST => RECYCLE_RST,
CK_P_BIT => SALS.SALS_PK,
ALU_CHK_LCH => sALU_CHK_LCH,
@ -800,37 +819,41 @@ MpxChnlCtrls: entity MpxFA port map (
SET_BUS_O_CTRL_LCH => SET_BUS_O_CTRL_LCH,
N1401_MODE => N1401_MODE,
-- 1050 attachment
N1050_INSTALLED => '1',
N1050_REQ_IN => '0',
N1050_OP_IN => '0',
N1050_CE_MODE => '0',
N1050_SEL_IN => '0',
N1050_SEL_O => '0',
N1050_INSTALLED => n1050_INSTALLED,
N1050_REQ_IN => n1050_REQ_IN,
N1050_OP_IN => n1050_OP_IN,
N1050_CE_MODE => n1050_CE_MODE,
N1050_SEL_IN => n1050_SEL_IN,
N1050_SEL_O => n1050_SEL_O,
P_1050_SEL_OUT => P_1050_SEL_OUT,
P_1050_SEL_IN => P_1050_SEL_IN,
MPX_METERING_IN => MPX_METERING_IN,
FT7_MPX_CHNL_IN => sFT7,
LOAD_IND => LOAD_IND,
SUPPR_CTRL_LCH => SUPPR_CTRL_LCH,
OP_OUT_SIGNAL => OP_OUT_SIG,
RECYCLE_RESET => RECYCLE_RST,
-- RECYCLE_RESET => RECYCLE_RST,
OP_OUT_SIG => OP_OUT_SIG,
SEL_O_FT6 => FT6,
-- N1050_SEL_OUT => N1050_SEL_OUT,
-- SUPPR_O => SUPPR_O ,
SUPPR_O_FT0 => FT0,
SUPPR_O => FT0 ,
-- SUPPR_O_FT0 => FT0,
-- OP_OUT => OP_OUT,
METERING_OUT => METERING_OUT,
CLOCK_OUT => CLOCK_OUT,
CLK => CLK,
DEBUG => DEBUG,
-- Mpx Indicators
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => ADDR_OUT,
ADDR_OUT => sADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT
);
);
ADDR_OUT <= sADDR_OUT;
end FMD;

496
FMD2030_UDC3.vhd Normal file
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@ -0,0 +1,496 @@
---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_UDC3.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console interface section
-- Will also include Selector Channel(s) eventually
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY udc3 IS
port
(
-- Inputs
E_SW_SEL_BUS : IN E_SW_BUS_Type;
USE_MANUAL_DECODER : IN STD_LOGIC;
USE_ALT_CA_DECODER, USE_BASIC_CA_DECO : IN STD_LOGIC;
GTD_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8);
GT_1050_TAGS_OUT : IN STD_LOGIC;
GT_1050_BUS_OUT : IN STD_LOGIC;
-- PCH_CONN_ENTRY : IN PCH_CONN;
P_1050_SEL_IN : IN STD_LOGIC;
P_1050_SEL_OUT : IN STD_LOGIC;
SUPPRESS_OUT : IN STD_LOGIC;
CK_SAL_P_BIT : IN STD_LOGIC;
RECYCLE_RESET : IN STD_LOGIC;
MPX_OPN_LT_GATE : IN STD_LOGIC;
ADDR_OUT : IN STD_LOGIC;
-- Outputs
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 111111111 when inactive
M_ASSM_BUS,N_ASSM_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
T_REQUEST : OUT STD_LOGIC;
n1050_INTRV_REQ : OUT STD_LOGIC;
TT6_POS_ATTN : OUT STD_LOGIC;
n1050_INSTALLED : OUT STD_LOGIC;
n1050_REQ_IN : OUT STD_LOGIC;
n1050_OP_IN : OUT STD_LOGIC;
n1050_CE_MODE : OUT STD_LOGIC;
n1050_SEL_O : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- Clocks
clk : IN STD_LOGIC;
Clock1ms : IN STD_LOGIC;
Clock60Hz : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END udc3;
ARCHITECTURE FMD OF udc3 IS
signal WRITE_LCH : STD_LOGIC;
signal RST_ATTACH : STD_LOGIC;
signal PUNCH_1_CLUTCH, RDR_1_CLUTCH : STD_LOGIC;
signal READ_CLK_INTLK_LCH : STD_LOGIC;
signal CRLF : STD_LOGIC;
signal CLOCK_1 : STD_LOGIC;
signal CLK_STT_RST : STD_LOGIC;
signal W_TIME,X_TIME,Y_TIME,Z_TIME : STD_LOGIC;
signal RD_OR_RD_INQ : STD_LOGIC;
signal RD_INLK_RST : STD_LOGIC;
signal WRITE_LCH_RST : STD_LOGIC;
signal TT2_POS_END : STD_LOGIC;
signal CE_DATA_ENTER_GT : STD_LOGIC;
signal CE_TA_DECODE : STD_LOGIC;
signal CE_RESET : STD_LOGIC;
signal RUN : STD_LOGIC;
signal TAGS_OUT_BUS : STD_LOGIC_VECTOR(0 to 7);
signal sn1050_CE_MODE : STD_LOGIC;
signal EXIT_MPLX_SHARE : STD_LOGIC;
signal RD_SHARE_REQ : STD_LOGIC;
signal WR_SHARE_REQ : STD_LOGIC;
signal CE_SEL_O : STD_LOGIC;
signal sn1050_INTRV_REQ : STD_LOGIC;
signal UNGATED_RUN : STD_LOGIC;
signal REQUEST_KEY : STD_LOGIC;
signal n1050_RST_LCH : STD_LOGIC;
signal HOME_RDR_START_LCH : STD_LOGIC;
signal HOME_RDR_STOP : STD_LOGIC;
signal PROCEED_LCH : STD_LOGIC;
signal MICRO_SHARE_LCH : STD_LOGIC;
signal RDR_ON_LCH : STD_LOGIC;
signal TA_REG_POS_4 : STD_LOGIC;
signal AUDIBLE_ALARM : STD_LOGIC;
signal TA_REG_POS_6_ATTENTION_RST : STD_LOGIC;
signal SHARE_REQ_RST : STD_LOGIC;
signal CPU_REQUEST_IN : STD_LOGIC;
signal sTT6_POS_ATTN : STD_LOGIC;
signal XLATE_UC : STD_LOGIC;
signal sn1050_OP_IN : STD_LOGIC;
signal SET_SHIFT_LCH : STD_LOGIC;
signal TA_REG_SET : STD_LOGIC;
signal n1050_OPER : STD_LOGIC;
signal READ_INQ : STD_LOGIC;
signal RD_SHARE_REQ_LCH : STD_LOGIC;
signal READ : STD_LOGIC;
signal RESTORE : STD_LOGIC;
signal OUTPUT_SEL_AND_READY : STD_LOGIC;
signal UC_CHARACTER, LC_CHARACTER : STD_LOGIC;
signal PCH_BITS : STD_LOGIC_VECTOR(0 to 6);
signal CE_GT_TA_OR_TE, CE_TE_DECODE : STD_LOGIC;
signal CE_RUN_MODE : STD_LOGIC;
signal CE_BITS : STD_LOGIC_VECTOR(0 to 7);
signal DATA_REG_BUS : STD_LOGIC_VECTOR(0 to 7);
signal TE_LCH : STD_LOGIC;
signal ALLOW_STROBE : STD_LOGIC;
signal GT_WRITE_REG : STD_LOGIC;
signal FORCE_SHIFT_CHAR, FORCE_LC_SHIFT : STD_LOGIC;
signal SET_LOWER_CASE : STD_LOGIC;
signal READY_SHARE : STD_LOGIC;
signal TT_BUS : STD_LOGIC_VECTOR(0 to 7);
signal WRITE_MODE : STD_LOGIC;
signal NPL_BITS : STD_LOGIC_VECTOR(0 to 7);
signal PTT_BITS : STD_LOGIC_VECTOR(0 to 6);
signal WRITE_UC : STD_LOGIC;
signal WR_STROBE : STD_LOGIC;
signal PCH_1_HOME : STD_LOGIC;
signal TT5_POS_INTRV_REQ : STD_LOGIC;
signal CPU_LINES_ENTRY : CONN_1050;
signal CE_MODE_AND_TE_LCH : STD_LOGIC;
signal CE_SEL_OUT : STD_LOGIC;
signal CE_TI_DECODE : STD_LOGIC;
signal CE_BUS : STD_LOGIC_VECTOR(0 to 7);
signal CE_DATA_ENTER_NC : STD_LOGIC;
signal GTD_TT3 : STD_LOGIC;
BEGIN
M_ASSM_BUS <= (others=>'0');
N_ASSM_BUS <= (others=>'0');
-- Fig 5-09C
n1050_TRANSLATE : entity n1050_TRANSLATE port map(
-- Inputs
DATA_REG_BUS => DATA_REG_BUS,
RDR_ON_LCH => RDR_ON_LCH,
PUNCH_1_CLUTCH_1050 => PUNCH_1_CLUTCH,
HOME_RDR_STT_LCH => HOME_RDR_START_LCH,
CLOCK_STT_RST => CLK_STT_RST,
RST_ATTACH => RST_ATTACH,
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
n1050_RST => n1050_RST_LCH,
ALLOW_STROBE => ALLOW_STROBE,
PROCEED_LCH => PROCEED_LCH,
SHARE_REQ_RST => SHARE_REQ_RST,
CE_RUN_MODE => CE_RUN_MODE,
CE_TI_DECODE => CE_TI_DECODE,
SET_LOWER_CASE => SET_LOWER_CASE,
n1050_RST_LCH => n1050_RST_LCH,
READY_SHARE => READY_SHARE,
-- Outputs
TT2_POS_END => TT2_POS_END,
XLATE_UC => XLATE_UC,
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH,
READ_SHARE_REQ => RD_SHARE_REQ,
WRITE_UC => WRITE_UC,
SET_SHIFT_LCH => SET_SHIFT_LCH,
PCH_1_HOME => PCH_1_HOME,
RUN => RUN,
UNGATED_RUN => UNGATED_RUN,
READ => READ,
READ_INQ => READ_INQ,
RD_OR_RD_INQ => RD_OR_RD_INQ,
LC_CHARACTER =>LC_CHARACTER,
UC_CHARACTER => UC_CHARACTER,
WRITE_LCH => WRITE_LCH,
WRITE_MODE => WRITE_MODE,
WRITE_STROBE => WR_STROBE,
WRITE_LCH_RST => WRITE_LCH_RST,
DEBUG => open
);
-- Fig 5-10A
n1050_CLOCK : entity n1050_CLOCK port map (
-- Inputs
WRITE_LCH => WRITE_LCH, -- 09CD2
READ_OR_READ_INQ => RD_OR_RD_INQ, -- 09CC5
RST_ATTACH => RST_ATTACH, -- 10BC2
PUNCH_1_CLUTCH => PUNCH_1_CLUTCH, -- 10DD5
READ_CLK_INTLK_LCH => READ_CLK_INTLK_LCH, -- 10BA2
RDR_1_CLUTCH => RDR_1_CLUTCH, -- 10DD5
CRLF => CRLF, -- ?
-- Outputs
CLOCK_1 => CLOCK_1, -- 10CD1 10CA4
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
CLK_STT_RST => CLK_STT_RST, -- 09CE1
clk => clk -- 50MHz
);
-- Fig 5-10B
n1050_TAGS : entity n1050_TAGS port map (
-- Inputs
RD_OR_RD_INQ => RD_OR_RD_INQ, -- 09CC5
Y_TIME => Y_TIME, -- 10AXX
RD_INLK_RST => RD_INLK_RST, -- 10DC5
WRITE_LCH_RST => WRITE_LCH_RST, -- 09CE2
PCH_1_CLUTCH => PUNCH_1_CLUTCH, -- 10DD5
TT2_POS_END => TT2_POS_END, -- 09CB5
WRITE_LCH => WRITE_LCH, -- 09CD2
Z_TIME => Z_TIME, -- 10AXX
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT, -- 10DA2
CE_TA_DECODE => CE_TA_DECODE, -- 10DA1
GT_1050_TAGS_OUT => GT_1050_TAGS_OUT, -- 10CE2
RECYCLE_RESET => RECYCLE_RESET, -- 04CA5
CE_RESET => CE_RESET, -- 10DC2
RUN => RUN, -- 09CE6
TT3_POS_1050_OPER => TT_BUS(3), -- 10DD4
TAGS_OUT_BUS => TAGS_OUT_BUS, -- 10CD1
n1050_CE_MODE => sn1050_CE_MODE, -- 10DB3
n1050_SEL_O => n1050_SEL_O, -- 08DD6
P_1050_SEL_IN => P_1050_SEL_IN, -- 08DC1
P_1050_SEL_OUT => P_1050_SEL_OUT, -- 08DD6
MPX_OPN_LCH_GT => MPX_OPN_LT_GATE, -- 08CE3
CK_SAL_P_BIT => CK_SAL_P_BIT, -- 01CXX
EXIT_MPLX_SHARE => EXIT_MPLX_SHARE, -- 10DB3
ADDR_OUT => ADDR_OUT, -- 08DA5
RD_SHARE_REQ => RD_SHARE_REQ, -- 09CC6
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH, -- 09CC6
SUPPRESS_OUT => SUPPRESS_OUT, -- 08DD6
WR_SHARE_REQ => WR_SHARE_REQ, -- 10CA6
CE_SEL_O => CE_SEL_O, -- 10DB2
INTRV_REQ => sn1050_INTRV_REQ, -- 10CD6
RDY_SHARE => READY_SHARE, -- 10CE6
UNGATED_RUN => UNGATED_RUN, -- 09CE6
REQUEST_KEY => REQUEST_KEY, -- 10DE5
-- Outputs
n1050_RST_LCH => n1050_RST_LCH, -- 10DF2 09CD1 10CA5 09CE5
HOME_RDR_START_LCH => HOME_RDR_START_LCH, -- 09CE4 09CE1 10DE2
HOME_RDR_STOP => HOME_RDR_STOP, -- 10DC5
PROCEED_LCH => PROCEED_LCH, -- 09CE4 10CC2 10DE2
MICRO_SHARE_LCH => MICRO_SHARE_LCH, -- 10DE2
RDR_ON_LCH => RDR_ON_LCH, -- 09CE4 10DE2 09CE1
TA_REG_POS_4 => TA_REG_POS_4, -- 10DE2
AUDIBLE_ALARM => AUDIBLE_ALARM, -- 14AXX
CR_LF => CRLF, -- 10AC1 10DE2
TA_REG_POS_6_ATTENTION_RST => TA_REG_POS_6_ATTENTION_RST, -- ---D4 10DE2 10CE5
CPU_LINES_TO_1050 => CPU_LINES_ENTRY, -- 10DE3
SHARE_REQ_RST => SHARE_REQ_RST, -- 09CC5 10CE4 10CA5
T_REQUEST => T_REQUEST, -- 07BD3 06BA3 07BB3
CPU_REQUEST_IN => CPU_REQUEST_IN, -- 10DE3
n1050_OP_IN => sn1050_OP_IN, -- 08DD4 10CA4
n1050_REQ_IN => n1050_REQ_IN, -- 08DD2
TT6_POS_ATTN => sTT6_POS_ATTN, -- 10DC4 04AB6
n1050_INSTALLED => n1050_INSTALLED, -- 08DC1
TA_REG_SET => TA_REG_SET,
RD_CLK_INLK_LCH => READ_CLK_INTLK_LCH,
RESTORE => RESTORE,
RST_ATTACH => RST_ATTACH,
DEBUG => DEBUG,
-- Clocks
clk => clk,
Clock1ms => Clock1ms,
Clock60Hz => Clock60Hz,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4
);
TT6_POS_ATTN <= sTT6_POS_ATTN;
n1050_OP_IN <= sn1050_OP_IN;
-- Fig 5-10C
n1050_DATA : entity n1050_DATA port map (
-- Inputs
E_SW_SEL_BUS => E_SW_SEL_BUS,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
GTD_CA_BITS => GTD_CA_BITS,
XLATE_UC => XLATE_UC,
WR_LCH => WRITE_LCH,
RUN => RUN,
PROCEED_LCH => PROCEED_LCH,
-- TT4_POS_HOME_STT => TT4_POS_HOME_STT,
RD_OR_RD_INQ => RD_OR_RD_INQ,
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
Z_BUS => Z_BUS,
CLOCK_1 => CLOCK_1,
PCH_1_CLUTCH => PUNCH_1_CLUTCH,
GT_1050_BUS_OUT => GT_1050_BUS_OUT,
GT_1050_TAGS_OUT => GT_1050_TAGS_OUT,
n1050_OP_IN => sn1050_OP_IN,
SET_SHIFT_LCH => SET_SHIFT_LCH,
TA_REG_SET => TA_REG_SET,
RST_ATTACH => RST_ATTACH,
n1050_OPER => n1050_OPER,
READ_INQ => READ_INQ,
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH,
READ => READ,
WRITE_MODE => WRITE_MODE,
RESTORE => RESTORE,
OUTPUT_SEL_AND_READY => OUTPUT_SEL_AND_READY,
SHARE_REQ_RST => SHARE_REQ_RST,
n1050_RST_LCH => n1050_RST_LCH,
RDR_1_CLUTCH => RDR_1_CLUTCH,
UC_CHARACTER => UC_CHARACTER,
LC_CHARACTER => LC_CHARACTER,
-- Z_BUS_0 => Z_BUS(0),
-- Z_BUS_3 => Z_BUS(3),
-- TT3_POS_1050_OPER => TT3_POS_1050_OPER,
TA_REG_POS_6_ATTN_RST => TA_REG_POS_6_ATTENTION_RST,
PCH_BITS => PCH_BITS,
-- CE controls
CE_GT_TA_OR_TE => CE_GT_TA_OR_TE,
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT,
CE_TE_DECODE => CE_TE_DECODE,
CE_RUN_MODE => CE_RUN_MODE,
n1050_CE_MODE => sn1050_CE_MODE,
CE_BITS => CE_BITS,
-- Outputs
A_REG_BUS => A_BUS,
DATA_REG_BUS => DATA_REG_BUS,
TAGS_OUT => TAGS_OUT_BUS,
NPL_BITS => NPL_BITS,
PTT_BITS => PTT_BITS,
TE_LCH => TE_LCH,
WR_SHARE_REQ => WR_SHARE_REQ,
ALLOW_STROBE => ALLOW_STROBE,
GT_WRITE_REG => GT_WRITE_REG,
FORCE_SHIFT_CHAR => FORCE_SHIFT_CHAR,
FORCE_LC_SHIFT => FORCE_LC_SHIFT,
SET_LOWER_CASE => SET_LOWER_CASE,
n1050_INTRV_REQ => sn1050_INTRV_REQ,
READY_SHARE => READY_SHARE,
TT5_POS_INTRV_REQ => TT5_POS_INTRV_REQ,
-- Buses
TT_BUS => TT_BUS,
GTD_TT3 => GTD_TT3,
DEBUG => open,
-- Clocks
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4
);
n1050_INTRV_REQ <= sn1050_INTRV_REQ;
-- Fig 5-10D
n1050_ATTACH : entity n1050_ATTACH port map (
-- Inputs
-- CE Cable
CE_CABLE_IN => open,
-- CE DATA BUS From 1050 DATA section
PTT_BITS => PTT_BITS,
DATA_REG => DATA_REG_BUS,
NPL_BITS => NPL_BITS,
-- Other stuff
TE_LCH => TE_LCH,
WRITE_UC => WRITE_UC,
XLATE_UC => XLATE_UC,
CPU_REQUEST_IN => CPU_REQUEST_IN,
n1050_OP_IN => sn1050_OP_IN,
HOME_RDR_STT_LCH => HOME_RDR_START_LCH,
RDR_ON_LCH => RDR_ON_LCH,
MICRO_SHARE_LCH => MICRO_SHARE_LCH,
PROCEED_LCH => PROCEED_LCH,
TA_REG_POS_4 => TA_REG_POS_4,
CR_LF => CRLF,
TA_REG_POS_6 => TA_REG_POS_6_ATTENTION_RST,
n1050_RST => n1050_RST_LCH,
GT_WR_REG => GT_WRITE_REG,
FORCE_LC_SHIFT => FORCE_LC_SHIFT,
FORCE_SHIFT_CHAR => FORCE_SHIFT_CHAR,
WR_STROBE => WR_STROBE,
PCH_1_HOME => PCH_1_HOME,
HOME_RDR_STOP => HOME_RDR_STOP,
TT2_POS_END => TT2_POS_END,
TT5_POS_INTRV_REQ => TT5_POS_INTRV_REQ,
TT6_POS_ATTN => sTT6_POS_ATTN,
CPU_LINES_ENTRY => CPU_LINES_ENTRY,
-- PCH_CONN_ENTRY => PCH_CONN_ENTRY,
RDR_1_CLUTCH => RDR_1_CLUTCH,
-- Outputs
-- CE Cable
CE_CABLE_OUT => open,
-- CE DATA BUS to 10C (1050 DATA)
CE_GT_TA_OR_TE => CE_GT_TA_OR_TE,
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT,
CE_TE_DECODE => CE_TE_DECODE,
CE_MODE_AND_TE_LCH => CE_MODE_AND_TE_LCH,
n1050_CE_MODE => sn1050_CE_MODE,
-- Other stuff
CE_SEL_OUT => CE_SEL_OUT,
CE_TI_DECODE => CE_TI_DECODE,
CE_RUN_MODE => CE_RUN_MODE,
CE_TA_DECODE => CE_TA_DECODE,
CE_BUS => CE_BUS,
EXIT_MPLX_SHARE => EXIT_MPLX_SHARE,
CE_DATA_ENTER_NC => CE_DATA_ENTER_NC,
-- TT3_POS_1050_OPER => TT_BUS(3),
-- TT4_POS_HOME_STT => TT_BUS(4),
OUTPUT_SEL_AND_RDY => OUTPUT_SEL_AND_READY,
n1050_OPER => n1050_OPER,
PUNCH_BITS => PCH_BITS,
READ_INTLK_RST => RD_INLK_RST,
PUNCH_1_CLUTCH => PUNCH_1_CLUTCH,
-- PCH_1_CLUTCH_1050 => PCH_1_CLUTCH_1050,
REQUEST_KEY => REQUEST_KEY,
-- RDR_1_CONN_EXIT => RDR_1_CONN_EXIT,
-- CPU_LINES_EXIT => n1050_CONTROL,
-- In/Out TT bus
TT_BUS => TT_BUS,
GTD_TT3 => GTD_TT3,
SerialInput => SerialInput,
SerialOutput => SerialOutput,
-- Clocks
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
clk => clk
);
n1050_CE_MODE <= sn1050_CE_MODE;
-- PCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050;
END FMD;

65
Gates2030.vhd
View File

@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -33,9 +33,10 @@
--
-- Revision History:
-- Revision 1.0
--
--
--
-- Initial release
-- Revision 1.1 2012-04-07
-- Add SingleShot (SS) and XilinxIOVector
-- Revise DelayRisingEdgeX implementation
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
@ -59,9 +60,11 @@ component FLVL is port(S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR);
function mux(sel : in STD_LOGIC; D : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function EvenParity(v : in STD_LOGIC_VECTOR) return STD_LOGIC;
component AR is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component SS is port( Clk : in STD_LOGIC; Count : in integer; D: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DEGLITCH is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DEGLITCH2 is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DelayRisingEdge is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component XilinxIOVector is port( I : in STD_LOGIC_VECTOR; T : in STD_LOGIC; O : out STD_LOGIC_VECTOR; IO : inout STD_LOGIC_VECTOR); end component;
end Gates_package;
LIBRARY ieee;
@ -346,6 +349,39 @@ end if;
end process;
end slt;
-- Simple single-shot (SS)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity SS is port( Clk : in STD_LOGIC; Count : in integer; D: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of SS is
signal C : integer;
begin
process(D,Clk)
begin
if (rising_edge(Clk)) then
if (C = 0) then
if D='1' then
C <= Count;
Q <= '1';
else
Q <= '0';
end if;
else
if (C = 1) then
Q <= '0';
if D='0' then
C <= 0;
end if;
else
C <= C - 1;
Q <= '1';
end if;
end if;
end if;
end process;
end slt;
-- Simple 1 cycle de-glitch
-- LIBRARY ieee;
-- USE ieee.std_logic_1164.all;
@ -387,24 +423,35 @@ USE ieee.std_logic_1164.all;
entity DelayRisingEdgeX is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of DelayRisingEdgeX is
signal Q1 : std_logic_vector(1 to 3) := "000";
signal Q1 : std_logic_vector(1 to 4) := "0000";
begin
process(D,Clk)
begin
if (rising_edge(Clk)) then
if (D='0') then
Q <= '0';
Q1 <= "000";
else if (D='1') and (Q1="111") then
Q1 <= "0000";
else if (D='1') and (Q1="1111") then
Q <= '1';
Q1 <= "111";
Q1 <= "1111";
else
Q <= '0';
Q1 <= Q1(2 to 3) & '1';
Q1 <= Q1(2 to 4) & '1';
end if;
end if;
end if;
end process;
end slt;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity XilinxIOVector is port( I : in STD_LOGIC_VECTOR(0 to 8); T : in STD_LOGIC; O : out STD_LOGIC_VECTOR(0 to 8); IO : inout STD_LOGIC_VECTOR(0 to 8)); end;
architecture slt of XilinxIOVector is
component IOBUF port (I, T: in std_logic; O: out std_logic; IO: inout std_logic); end component;
begin
word_generator: for b in 0 to 8 generate
begin
U1: IOBUF port map (I => I(b), T => T, O => O(b), IO => IO(b));
end generate;
end slt;

262
PROM_reader_serial.vhd Normal file
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@ -0,0 +1,262 @@
--*****************************************************************************************
--**
--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
--** provided to you "as is". Xilinx and its licensors make and you
--** receive no warranties or conditions, express, implied, statutory
--** or otherwise, and Xilinx specifically disclaims any implied
--** warranties of merchantability, non-infringement, or fitness for a
--** particular purpose. Xilinx does not warrant that the functions
--** contained in these designs will meet your requirements, or that the
--** operation of these designs will be uninterrupted or error free, or
--** that defects in the Designs will be corrected. Furthermore, Xilinx
--** does not warrant or make any representations regarding use or the
--** results of the use of the designs in terms of correctness, accuracy,
--** reliability, or otherwise.
--**
--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
--** liable for any loss of data, lost profits, cost or procurement of
--** substitute goods or services, or for any special, incidental,
--** consequential, or indirect damages arising from the use or operation
--** of the designs or accompanying documentation, however caused and on
--** any theory of liability. This limitation will apply even if Xilinx
--** has been advised of the possibility of such damage. This limitation
--** shall apply not-withstanding the failure of the essential purpose of
--** any limited remedies herein.
--**
--*****************************************************************************************
-- MODULE : PROM_reader_serial.vhd
-- AUTHOR : Stephan Neuhold
-- VERSION : v1.00
--
--
-- REVISION HISTORY:
-- -----------------
-- No revisions
--
--
-- FUNCTION DESCRIPTION:
-- ---------------------
-- This module provides the control state machine
-- for reading data from the PROM. This includes
-- searching for synchronisation patterns, retrieving
-- data, resetting the PROMs address counter.
--***************************
--* Library declarations
--***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--***********************
--* Entity declaration
--***********************
entity PROM_reader_serial is
generic(
length : integer := 5;
frequency : integer := 50
);
port(
clock : in std_logic;
reset : in std_logic; --active high
read : in std_logic; --active low
next_sync : in std_logic; --active low
din : in std_logic;
sync_pattern : in std_logic_vector((2**length) - 1 downto 0);
cclk : out std_logic;
sync : out std_logic; --active low
data_ready : out std_logic; --active low
reset_prom : out std_logic; --active high
dout : out std_logic_vector(7 downto 0)
);
end PROM_reader_serial;
architecture Behavioral of PROM_reader_serial is
component clock_management
generic(
length : integer := 5;
frequency : integer := 50
);
port(
clock : in std_logic;
enable : in std_logic;
read_enable : out std_logic;
cclk : out std_logic
);
end component;
component shift_compare_serial
generic(
length : integer := 5
);
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
din : in std_logic;
b : in std_logic_vector((2**length) - 1 downto 0);
eq : out std_logic;
din_shifted : out std_logic_vector(7 downto 0)
);
end component;
type state_type is (Look4Sync, Wait4Active, GetData, PresentData);
signal current_state : state_type;
signal count : std_logic_vector(length downto 0);
signal din_read_enable : std_logic;
signal sync_found : std_logic;
signal data : std_logic_vector(7 downto 0);
signal sync_int : std_logic;
signal cclk_on : std_logic;
signal reset_n : std_logic;
begin
--Clock generation and clock enable generation
Clock_Manager: clock_management
generic map(
length => length,
frequency => frequency
)
port map(
clock => clock,
enable => cclk_on,
read_enable => din_read_enable,
cclk => cclk
);
--Shift and compare operation
Shift_And_Compare: shift_compare_serial
generic map(
length => length
)
port map(
clock => clock,
reset => reset,
enable => din_read_enable,
din => din,
b => sync_pattern,
eq => sync_found,
din_shifted => data
);
--State machine
process (clock, reset, current_state, sync_int, read, count,
data, sync_found)
begin
if (reset = '1') then
current_state <= Look4Sync; --this can be changed to Wait4Active so that the FPGA doesnt go looking for data immediately after config
dout <= (others => '0');
count <= (others => '0');
sync_int <= '0';
data_ready <= '1';
reset_PROM <= '0';
cclk_on <= '1';
elsif rising_edge(clock) then
case current_state is
--*************************************************************
--* This state clocks in one bit of data at a time from the
--* PROM. With every new bit clocked in a comparison is done
--* to check whether it matches the synchronisation pattern.
--* If the pattern is found then a further bits are read
--* from the PROM to provide the first byte of data appearing
--* after the synchronisation pattern.
--*************************************************************
when Look4Sync =>
count <= (others => '0');
data_ready <= '1';
sync_int <= '0';
reset_PROM <= '1';
if (sync_found = '1') then
current_state <= Wait4Active;
sync_int <= '1';
cclk_on <= '0';
end if;
--*********************************************************
--* At this point the state machine waits for user input.
--* If the user pulses the "read" signal then 8 bits of
--* are retrieved from the PROM. If the user wants to
--* look for another synchronisation pattern and pulses
--* the "next_sync" signal, then the state machine goes
--* into the "Look4Sync" state.
--*********************************************************
when Wait4Active =>
count <= (others => '0');
data_ready <= '1';
if (read = '0' or sync_int = '1') then
current_state <= GetData;
cclk_on <= '1';
end if;
if (next_sync = '0') then
current_state <= Look4Sync;
cclk_on <= '1';
end if;
--*********************************************************
--* This state gets the data from the PROM. If the
--* synchronisation pattern has just been found then
--* enough data is retrieved to present the first
--* 8 bits after the pattern. This is dependant on the
--* synchronisation pattern length.
--* If the synchronisation pattern has already been found
--* previously then only the next 8 bits of data are
--* retrieved.
--*********************************************************
when GetData =>
if (din_read_enable = '1') then
count <= count + 1;
if (sync_int = '1') then
if (count = (2**length) - 1) then
current_state <= PresentData;
sync_int <= '0';
cclk_on <= '0';
end if;
else
if (count = 7) then
current_state <= PresentData;
sync_int <= '0';
cclk_on <= '0';
end if;
end if;
end if;
--*******************************************************
--* This state tells the user that 8 bits of data have
--* been retrieved and is presented on the "dout" port.
--* The "Wait4Active" state is then entered to wait for
--* another user request.
--*******************************************************
when PresentData =>
dout <= data;
data_ready <= '0';
current_state <= Wait4Active;
when others =>
null;
end case;
end if;
sync <= not sync_found;
end process;
end Behavioral;

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IBM2030
=======
An IBM System/360 Model 30 in VHDL
There are two main components to this release:
VHDL for the CPU (with 8k storage) and Multiplexer channel
The microcode image (4k x 55)
I am not claiming copyright to the microcode image - this is based on IBM manuals from 1964-1965 which may or may not be copyrighted themselves.
The VHDL is based on the IBM Maintenance Diagram Manual (MDM), which can be found on Bitsavers.
As supplied, the compiled system is suitable for a Digilent Spartan 3 board with a 1000K device, see http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD
It uses the following I/O:
VGA output (8-colour, 3-bit)
Parallel I/O for switch scanning (10 out, 14 in)
On-board pushbutton inputs (4)
On-board slide switch inputs (8)
On-board LED outputs (8)
If using an alternative board, it may be sufficient to modify the UCF file to reallocate inputs and outputs
These files can be compiled using the Xilinx ISE Webpack (and presumably other versions of the Xilinx suite). I have not tried compiling them with other VHDL compilers.
Apologies for the varied quality of the VHDL. This project has taken over 5 years and I have not necessarily re-visited code that was written early on. So there is a variety of styles and conventions. In my defence, it works (or seems to).
Lawrence Wilkinson
lawrence@ljw.me.uk
2010/07/16

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------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral;

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#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#define ccrosLineSize 100
#define versions " |004|005|006|007|010|014|025|A20"
/*
#AAA CN CH CL CM CU CA CB CK CD CF CG CV CC CS AAASAKPK
102 F3 0001 0001 110 01 ???? ?? 0010 0110 000 00 00 000 0000 ? 0 0 1 # QA001:C2
*/
struct ccrosLayout {
char space1;
char ADDR[3];
char space2[2];
char CN[2];
char space3;
char CH[4];
char space4;
char CL[4];
char space5;
char CM[3];
char space6;
char CU[2];
char space7;
char CA[4];
char space8;
char CB[2];
char space9;
char CK[4];
char space10;
char CD[4];
char space11;
char CF[3];
char space12;
char CG[2];
char space13;
char CV[2];
char space14;
char CC[3];
char space15;
char CS[4];
char space16;
char AA;
char space17;
char AS;
char space18;
char AK;
char space19;
char PK;
char space20;
char comment[11]; /* # QANNN:RN- */
char version[3];
} ccrosLine;
typedef struct {
int address;
char ccros[56]; /* Final char is NUL */
} ccrosEntry;
ccrosEntry ccros[4096];
int ccrosEntryCount;
char *flag;
char *ptr;
int i;
char thisVersion[4];
int htoi(char *hex, int length) {
int value = 0;
char ch;
for (;length>0;length--) {
ch = *(hex++);
if (ch >= '0' && ch <= '9')
value = (value << 4) + (ch - '0');
else if (ch >= 'A' && ch <= 'F')
value = (value << 4) + (ch - 'A' + 10);
else if (ch >= 'a' && ch <= 'f')
value = (value << 4) + (ch - 'a' + 10);
else
return value;
}
}
char * itob(int value, char *buffer, int length) {
char *ptr;
ptr = buffer + length;
for (;length>0;length--) {
*--ptr = '0' + (value & 1);
value = value >> 1;
}
return buffer;
}
char parity(char *buffer, int length, char start) {
char result = start;
for (;length>0;length--) {
result^=(*buffer++ & 1);
}
return result;
}
main (int argc, char *argv[]) {
if ((argc==2) && (strcmp(argv[1],"-v")==0)) {
printf("CCROS file converter 2012-04-07\n");
exit(0);
}
ccrosEntryCount = 0;
while (1) {
ccrosLine.version[0]=' ';
ccrosLine.version[1]=' ';
ccrosLine.version[2]=' ';
flag = gets((char*)&ccrosLine);
if (flag != NULL) {
thisVersion[0]=ccrosLine.version[0];
thisVersion[1]=ccrosLine.version[1];
thisVersion[2]=ccrosLine.version[2];
thisVersion[3]='\0';
if (ccrosLine.space1=='#') {
/* Ignore comment line */
}
else if ( (ccrosLine.space1 !=' ') | (ccrosLine.space2[0] !=' ') | (ccrosLine.space2[1] !=' ') | (ccrosLine.space3 !=' ') | (ccrosLine.space4 !=' ') | (ccrosLine.space5 !=' ')
| (ccrosLine.space6 !=' ') | (ccrosLine.space7 !=' ') | (ccrosLine.space8 !=' ') | (ccrosLine.space9 !=' ') | (ccrosLine.space10!=' ')
| (ccrosLine.space11!=' ') | (ccrosLine.space12!=' ') | (ccrosLine.space13!=' ') | (ccrosLine.space14!=' ') | (ccrosLine.space15!=' ')
| (ccrosLine.space16!=' ') | (ccrosLine.space17!=' ') | (ccrosLine.space18!=' ') | (ccrosLine.space19!=' ') | (ccrosLine.space20!=' ')) {
/* Skip invalid line */
printf("Line format error\r\n");
puts((char*)&ccrosLine);
printf("\r\n");
exit(1);
}
else if (strstr(versions,(char*)&thisVersion[0])==NULL) {
/* Skip it */
}
else {
char cnBinary[9];
cnBinary[8]='\0';
char addrBinary[13];
addrBinary[12]='\0';
/* Handle CCROS line - convert to a 56-bit binary string in the same order */
ccros[ccrosEntryCount].address = htoi(ccrosLine.ADDR,3);
itob(ccros[ccrosEntryCount].address,addrBinary,12);
ccros[ccrosEntryCount].ccros[55] = '\0';
/* Generate binary from top 6 bits of CN */
itob(htoi(ccrosLine.CN,2),cnBinary,8);
/* 0 (PN) is calculated later */
ccros[ccrosEntryCount].ccros[0] = '0';
ccros[ccrosEntryCount].ccros[1] = cnBinary[0];
ccros[ccrosEntryCount].ccros[2] = cnBinary[1];
ccros[ccrosEntryCount].ccros[3] = cnBinary[2];
ccros[ccrosEntryCount].ccros[4] = cnBinary[3];
ccros[ccrosEntryCount].ccros[5] = cnBinary[4];
ccros[ccrosEntryCount].ccros[6] = cnBinary[5];
/* 7 (PS) and 8 (PA) are calculated later */
ccros[ccrosEntryCount].ccros[7] = '0';
ccros[ccrosEntryCount].ccros[8] = '0';
ccros[ccrosEntryCount].ccros[9] = ccrosLine.CH[0];
ccros[ccrosEntryCount].ccros[10] = ccrosLine.CH[1];
ccros[ccrosEntryCount].ccros[11] = ccrosLine.CH[2];
ccros[ccrosEntryCount].ccros[12] = ccrosLine.CH[3];
ccros[ccrosEntryCount].ccros[13] = ccrosLine.CL[0];
ccros[ccrosEntryCount].ccros[14] = ccrosLine.CL[1];
ccros[ccrosEntryCount].ccros[15] = ccrosLine.CL[2];
ccros[ccrosEntryCount].ccros[16] = ccrosLine.CL[3];
ccros[ccrosEntryCount].ccros[17] = ccrosLine.CM[0];
ccros[ccrosEntryCount].ccros[18] = ccrosLine.CM[1];
ccros[ccrosEntryCount].ccros[19] = ccrosLine.CM[2];
ccros[ccrosEntryCount].ccros[20] = ccrosLine.CU[0];
ccros[ccrosEntryCount].ccros[21] = ccrosLine.CU[1];
ccros[ccrosEntryCount].ccros[22] = ccrosLine.CA[0];
ccros[ccrosEntryCount].ccros[23] = ccrosLine.CA[1];
ccros[ccrosEntryCount].ccros[24] = ccrosLine.CA[2];
ccros[ccrosEntryCount].ccros[25] = ccrosLine.CA[3];
ccros[ccrosEntryCount].ccros[26] = ccrosLine.CB[0];
ccros[ccrosEntryCount].ccros[27] = ccrosLine.CB[1];
ccros[ccrosEntryCount].ccros[28] = ccrosLine.CK[0];
ccros[ccrosEntryCount].ccros[29] = ccrosLine.CK[1];
ccros[ccrosEntryCount].ccros[30] = ccrosLine.CK[2];
ccros[ccrosEntryCount].ccros[31] = ccrosLine.CK[3];
ccros[ccrosEntryCount].ccros[32] = ccrosLine.PK;
/* 32 (PC) is calculated later */
ccros[ccrosEntryCount].ccros[33] = '0';
ccros[ccrosEntryCount].ccros[34] = ccrosLine.CD[0];
ccros[ccrosEntryCount].ccros[35] = ccrosLine.CD[1];
ccros[ccrosEntryCount].ccros[36] = ccrosLine.CD[2];
ccros[ccrosEntryCount].ccros[37] = ccrosLine.CD[3];
ccros[ccrosEntryCount].ccros[38] = ccrosLine.CF[0];
ccros[ccrosEntryCount].ccros[39] = ccrosLine.CF[1];
ccros[ccrosEntryCount].ccros[40] = ccrosLine.CF[2];
ccros[ccrosEntryCount].ccros[41] = ccrosLine.CG[0];
ccros[ccrosEntryCount].ccros[42] = ccrosLine.CG[1];
ccros[ccrosEntryCount].ccros[43] = ccrosLine.CV[0];
ccros[ccrosEntryCount].ccros[44] = ccrosLine.CV[1];
ccros[ccrosEntryCount].ccros[45] = ccrosLine.CC[0];
ccros[ccrosEntryCount].ccros[46] = ccrosLine.CC[1];
ccros[ccrosEntryCount].ccros[47] = ccrosLine.CC[2];
ccros[ccrosEntryCount].ccros[48] = ccrosLine.CS[0];
ccros[ccrosEntryCount].ccros[49] = ccrosLine.CS[1];
ccros[ccrosEntryCount].ccros[50] = ccrosLine.CS[2];
ccros[ccrosEntryCount].ccros[51] = ccrosLine.CS[3];
ccros[ccrosEntryCount].ccros[52] = ccrosLine.AA;
ccros[ccrosEntryCount].ccros[53] = ccrosLine.AS;
ccros[ccrosEntryCount].ccros[54] = ccrosLine.AK;
/* Now change any ? to 0 */
for (ptr=&ccros[ccrosEntryCount].ccros[0];ptr<=&ccros[ccrosEntryCount].ccros[54];ptr++)
if (*ptr=='?') *ptr='0';
/* PA */
ccros[ccrosEntryCount].ccros[8] = parity(addrBinary,12,'1');
/* PN = CN */
ccros[ccrosEntryCount].ccros[0] = parity((char*)&ccros[ccrosEntryCount].ccros[1],6,'1');
/* PS = PA CH CL CM CU CA CB CK PK AA AK */
ccros[ccrosEntryCount].ccros[7] = parity((char*)&ccros[ccrosEntryCount].ccros[8],25,
parity((char*)&ccros[ccrosEntryCount].ccros[52],1,
parity((char*)&ccros[ccrosEntryCount].ccros[54],1,'1'
)
)
);
/* PC = CD CF CG CV CC CS AS */
ccros[ccrosEntryCount].ccros[33] = parity((char*)&ccros[ccrosEntryCount].ccros[34],18,
parity((char*)&ccros[ccrosEntryCount].ccros[53],1,'1'
)
);
/* BA0 flip PA & PC */
if (ccros[ccrosEntryCount].address==0xBA0) {
ccros[ccrosEntryCount].ccros[8] = ccros[ccrosEntryCount].ccros[8] ^ 1;
ccros[ccrosEntryCount].ccros[33] = ccros[ccrosEntryCount].ccros[33] ^ 1;
}
/* B60 flip PN, PS, PA & PC */
if (ccros[ccrosEntryCount].address==0xB60) {
ccros[ccrosEntryCount].ccros[0] = ccros[ccrosEntryCount].ccros[0] ^ 1;
ccros[ccrosEntryCount].ccros[7] = ccros[ccrosEntryCount].ccros[7] ^ 1;
ccros[ccrosEntryCount].ccros[8] = ccros[ccrosEntryCount].ccros[8] ^ 1;
ccros[ccrosEntryCount].ccros[33] = ccros[ccrosEntryCount].ccros[33] ^ 1;
}
ccrosEntryCount++;
}
}
else
break;
}
/* Now output */
for (i=0;i<ccrosEntryCount;i++) {
printf("16#%03x# => \"%s\",\r\n",ccros[i].address,(char*)&ccros[i].ccros[0]);
}
}

3434
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142
clock_management.vhd Normal file
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@ -0,0 +1,142 @@
--*****************************************************************************************
--**
--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
--** provided to you "as is". Xilinx and its licensors make and you
--** receive no warranties or conditions, express, implied, statutory
--** or otherwise, and Xilinx specifically disclaims any implied
--** warranties of merchantability, non-infringement, or fitness for a
--** particular purpose. Xilinx does not warrant that the functions
--** contained in these designs will meet your requirements, or that the
--** operation of these designs will be uninterrupted or error free, or
--** that defects in the Designs will be corrected. Furthermore, Xilinx
--** does not warrant or make any representations regarding use or the
--** results of the use of the designs in terms of correctness, accuracy,
--** reliability, or otherwise.
--**
--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
--** liable for any loss of data, lost profits, cost or procurement of
--** substitute goods or services, or for any special, incidental,
--** consequential, or indirect damages arising from the use or operation
--** of the designs or accompanying documentation, however caused and on
--** any theory of liability. This limitation will apply even if Xilinx
--** has been advised of the possibility of such damage. This limitation
--** shall apply not-withstanding the failure of the essential purpose of
--** any limited remedies herein.
--**
--*****************************************************************************************
-- MODULE : clock_management.vhd
-- AUTHOR : Stephan Neuhold
-- VERSION : v1.00
--
--
-- REVISION HISTORY:
-- -----------------
-- No revisions
--
--
-- FUNCTION DESCRIPTION:
-- ---------------------
-- This module generates an enable signal for
-- the shift register and comparator. It also
-- generates the clock signal that is connected
-- to the PROM.
-- The enable and clock signals are generated
-- based on the "frequency" generic entered for
-- the system clock.
-- The clock signal is only generated at the
-- appropriate times. All other states the clock
-- signal is kept at a logic high. The PROMs
-- address counter only increments on a rising
-- edge of this clock.
--***************************
--* Library declarations
--***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--***********************
--* Entity declaration
--***********************
entity clock_management is
generic(
length : integer := 5;
frequency : integer := 50
);
port(
clock : in std_logic;
enable : in std_logic;
read_enable : out std_logic;
cclk : out std_logic
);
end clock_management;
architecture Behavioral of clock_management is
signal cclk_int : std_logic := '1';
signal enable_cclk : std_logic;
signal SRL_length : std_logic_vector(3 downto 0);
signal temp : integer := (frequency / 20) - 1;
begin
--***************************************************
--* The length of the SRL16 is based on the system
--* clock frequency entered. This frequency is then
--* "divided" down to approximately 10MHz.
--***************************************************
SRL_length <= conv_std_logic_vector(temp, length - 1);
Divider0: SRL16
generic map(
init => X"0001"
)
port map(
clk => clock,
d => enable_cclk,
a0 => SRL_length(0),
a1 => SRL_length(1),
a2 => SRL_length(2),
a3 => SRL_length(3),
q => enable_cclk
);
--***************************************************
--* This process generates the enable signal for
--* the shift register and the comparator. It also
--* generates the clock signal used to increment
--* the PROMs address counter.
--***************************************************
process(clock, enable_cclk, enable, cclk_int)
begin
if rising_edge(clock) then
if (enable = '1') then
if (enable_cclk = '1') then
cclk_int <= not cclk_int;
end if;
if (enable_cclk = '1' and cclk_int = '1') then
read_enable <= '1';
else
read_enable <= '0';
end if;
else
cclk_int <= '1';
end if;
end if;
cclk <= cclk_int;
end process;
end Behavioral;

110
digilentSP3.ucf
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@ -2,7 +2,8 @@
# pin locations
# Original by Pierre Langlois, 2004/07/22
# minimal translation by Capt. LeSauvage 2004/09/23
# LJW2030 version by Lawrence Wilkinson, 2010/07/16
# LJW2030 V1.0 by Lawrence Wilkinson, 2010/07/16
# V1.1 2012-04-07
#
# Remove the comment symbols (#) in front of the desired lines.
# The names of the ports must match exactly between this file and the design.
@ -126,52 +127,54 @@ NET "ma2_db5" PULLDOWN;
#NET "ma2_reset" PULLDOWN;
#NET "ma2_int" LOC="D9"; # Check Reset
#NET "ma2_int" PULLDOWN;
#NET "progb" LOC="B3";
#NET "fpgadone" LOC="R14";
#NET "fpgainitb" LOC="N9";
#NET "fpgacclk" LOC="T15";
#NET "din" LOC="M11";
#A3
# SRAM
# NET "sramaddr<17>" LOC="L3";
# NET "sramaddr<16>" LOC="K5";
# NET "sramaddr<15>" LOC="K3";
# NET "sramaddr<14>" LOC="J3";
# NET "sramaddr<13>" LOC="J4";
# NET "sramaddr<12>" LOC="H4";
# NET "sramaddr<11>" LOC="H3";
# NET "sramaddr<10>" LOC="G5";
# NET "sramaddr<09>" LOC="E4";
# NET "sramaddr<08>" LOC="E3";
# NET "sramaddr<07>" LOC="F4";
# NET "sramaddr<06>" LOC="F3";
# NET "sramaddr<05>" LOC="G4";
# NET "sramaddr<04>" LOC="L4";
# NET "sramaddr<03>" LOC="M3";
# NET "sramaddr<02>" LOC="M4";
# NET "sramaddr<01>" LOC="N3";
# NET "sramaddr<00>" LOC="L5";
# NET "srama<15>" LOC="R1";
# NET "srama<14>" LOC="P1";
# NET "srama<13>" LOC="L2";
# NET "srama<12>" LOC="J2";
# NET "srama<11>" LOC="H1";
# NET "srama<10>" LOC="F2";
# NET "srama<09>" LOC="P8";
# NET "srama<08>" LOC="D3";
# NET "srama<07>" LOC="B1";
# NET "srama<06>" LOC="C1";
# NET "srama<05>" LOC="C2";
# NET "srama<04>" LOC="R5";
# NET "srama<03>" LOC="T5";
# NET "srama<02>" LOC="R6";
# NET "srama<01>" LOC="T8";
# NET "srama<00>" LOC="N7";
# NET "sramace" LOC="P7";
# NET "sramaub" LOC="T4";
# NET "sramalb" LOC="P6";
NET "sramaddr<17>" LOC="L3";
NET "sramaddr<16>" LOC="K5";
NET "sramaddr<15>" LOC="K3";
NET "sramaddr<14>" LOC="J3";
NET "sramaddr<13>" LOC="J4";
NET "sramaddr<12>" LOC="H4";
NET "sramaddr<11>" LOC="H3";
NET "sramaddr<10>" LOC="G5";
NET "sramaddr<9>" LOC="E4";
NET "sramaddr<8>" LOC="E3";
NET "sramaddr<7>" LOC="F4";
NET "sramaddr<6>" LOC="F3";
NET "sramaddr<5>" LOC="G4";
NET "sramaddr<4>" LOC="L4";
NET "sramaddr<3>" LOC="M3";
NET "sramaddr<2>" LOC="M4";
NET "sramaddr<1>" LOC="N3";
NET "sramaddr<0>" LOC="L5";
#NET "srama<15>" LOC="R1";
#NET "srama<15>" PULLDOWN;
#NET "srama<14>" LOC="P1";
#NET "srama<14>" PULLDOWN;
#NET "srama<13>" LOC="L2";
#NET "srama<13>" PULLDOWN;
#NET "srama<12>" LOC="J2";
#NET "srama<12>" PULLDOWN;
#NET "srama<11>" LOC="H1";
#NET "srama<11>" PULLDOWN;
#NET "srama<10>" LOC="F2";
#NET "srama<10>" PULLDOWN;
#NET "srama<9>" LOC="P8";
#NET "srama<9>" PULLDOWN;
NET "srama<8>" LOC="D3";
NET "srama<7>" LOC="B1";
NET "srama<6>" LOC="C1";
NET "srama<5>" LOC="C2";
NET "srama<4>" LOC="R5";
NET "srama<3>" LOC="T5";
NET "srama<2>" LOC="R6";
NET "srama<1>" LOC="T8";
NET "srama<0>" LOC="N7";
NET "sramace" LOC="P7";
NET "sramaub" LOC="T4";
NET "sramalb" LOC="P6";
# NET "sramb<15>" LOC="N1";
# NET "sramb<14>" LOC="M1";
# NET "sramb<13>" LOC="K2";
@ -190,9 +193,26 @@ NET "ma2_db5" PULLDOWN;
# NET "sramb<00>" LOC="P2";
# NET "srambce" LOC="N5";
# NET "srambub" LOC="R4";
# NET "sramblb" LOC="P5";
# NET "sramblb" LOC="P5";
NET "sramwe" LOC="G3";
NET "sramoe" LOC="K4";
# For the other peripherals and ports listed here,
# consult the Xilinx documentation.
# RS-232 port
# RS-232 port
NET "serialRx" LOC="T13";
NET "serialTx" LOC="R13";
# expansion connectors
#
#
# XCF04S Serial PROM connections
#
NET "din" LOC = "M11";
NET "reset_prom" LOC = "N9";
NET "rclk" LOC = "A14";
#NET "progb" LOC="B3";
#NET "fpgadone" LOC="R14";
#NET "fpgacclk" LOC="T15";

894
ibm2030-cpu.vhd Normal file
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@ -0,0 +1,894 @@
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: cpu.vhd
-- Creation Date: 22:15:23 2010-06-30
-- Description:
-- Top level of the CPU proper, combining all the various modules
-- including Processor, Storage, Multiplexor and (eventually) Selector(s)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity cpu is
Port (
WX_IND : OUT std_logic_vector(0 to 12);
W_IND_P : OUT std_logic;
X_IND_P : OUT std_logic;
IND_SALS : OUT SALS_Bus;
IND_EX,IND_CY_MATCH,IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : OUT STD_LOGIC;
IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
IND_MSDR_P : OUT STD_LOGIC;
IND_OPNL_IN : OUT STD_LOGIC;
IND_ADDR_IN : OUT STD_LOGIC;
IND_STATUS_IN : OUT STD_LOGIC;
IND_SERV_IN : OUT STD_LOGIC;
IND_SEL_OUT : OUT STD_LOGIC;
IND_ADDR_OUT : OUT STD_LOGIC;
IND_CMMD_OUT : OUT STD_LOGIC;
IND_SERV_OUT : OUT STD_LOGIC;
IND_SUPPR_OUT : OUT STD_LOGIC;
IND_FO : OUT STD_LOGIC_VECTOR(0 to 7);
IND_FO_P: OUT STD_LOGIC;
IND_A : OUT STD_LOGIC_VECTOR(0 to 8);
IND_B : OUT STD_LOGIC_VECTOR(0 to 8);
IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8);
IND_M : OUT STD_LOGIC_VECTOR(0 to 8);
IND_N : OUT STD_LOGIC_VECTOR(0 to 8);
IND_MAIN_STG : OUT STD_LOGIC;
IND_LOC_STG : OUT STD_LOGIC;
IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG : OUT STD_LOGIC;
IND_CHK_B_REG : OUT STD_LOGIC;
IND_CHK_STOR_ADDR : OUT STD_LOGIC;
IND_CHK_CTRL_REG : OUT STD_LOGIC;
IND_CHK_ROS_SALS : OUT STD_LOGIC;
IND_CHK_ROS_ADDR : OUT STD_LOGIC;
IND_CHK_STOR_DATA : OUT STD_LOGIC;
IND_CHK_ALU : OUT STD_LOGIC;
IND_SYST : OUT STD_LOGIC;
IND_MAN : OUT STD_LOGIC;
IND_WAIT : OUT STD_LOGIC;
IND_TEST : OUT STD_LOGIC;
IND_LOAD : OUT STD_LOGIC;
SW_START,SW_LOAD,SW_SET_IC,SW_STOP,SW_POWER_OFF : IN std_logic;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
SW_LAMP_TEST,SW_DSPLY,SW_STORE,SW_SYS_RST : IN STD_LOGIC;
SW_CHK_RST,SW_ROAR_RST,SW_CHK_RESTART,SW_DIAGNOSTIC : IN STD_LOGIC;
SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE,SW_ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,SW_ROAR_STOP : IN STD_LOGIC;
SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : IN STD_LOGIC;
SW_INTRP_TIMER, SW_CONS_INTRP : IN STD_LOGIC;
SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
E_SW : E_SW_BUS_Type;
-- External MPX connections
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
MPX_TAGS_I : IN MPX_TAGS_IN;
-- Storage (RAM) interface
StorageIn : IN STORAGE_IN_INTERFACE;
StorageOut : OUT STORAGE_OUT_INTERFACE;
-- PCH_CONN_ENTRY : IN PCH_CONN;
-- RDR_1_CONN_EXIT : OUT RDR_CONN;
-- n1050_CONTROL : OUT CONN_1050;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
DEBUG : INOUT DEBUG_BUS;
USE_MAN_DECODER_PWR : OUT STD_LOGIC;
Clock1ms : IN STD_LOGIC;
N60_CY_TIMER_PULSE : IN STD_LOGIC;
M_CONV_OSC : OUT STD_LOGIC;
SwSlow : in std_logic;
clk : in std_logic);
end cpu;
architecture FMD of cpu is
-- Outputs from UDC1 (5-01 through 5-05)
signal sSALS : SALS_Bus;
signal CTRL : CTRL_REG;
signal T1,T2,T3,T4 : std_logic;
signal SEL_T1, SEL_T3, SEL_T4 : std_logic;
signal P1,P2,P3,P4 : std_logic;
signal A_BUS1, B_BUS : std_logic_vector(0 to 8);
signal CLOCK_START : std_logic;
signal CLOCK_ON : std_logic;
signal STORE_S_REG_RST : std_logic; -- 03DC2
signal CTRL_REG_RST : std_logic; -- 01CB2
signal TO_KEY_SW : std_logic;
signal METERING_OUT : std_logic;
signal GT_1050_TAGS : std_logic;
signal GT_1050_BUS : std_logic;
signal SET_IND_ROSAR : STD_LOGIC;
signal GT_LOCAL_STORAGE : STD_LOGIC;
signal GT_T_REG_TO_MN : STD_LOGIC;
signal GT_CK_TO_MN : STD_LOGIC;
signal N_STACK_MEM_SELECT : STD_LOGIC;
signal WX_CHK : STD_LOGIC;
-- Outputs from UDC2 (5-06 through 5-09C)
signal Z_BUS,R : std_logic_vector(0 to 8);
signal MN : std_logic_vector(0 to 15);
signal CLOCK_OFF : std_logic;
signal A_REG_PC : std_logic;
signal MN_PC : std_logic;
signal Z0_BUS_0 : std_logic;
signal Z_0 : std_logic;
signal N_CTRL_N : std_logic;
signal ALU_CHK_LCH : std_logic;
signal SELECT_CPU_BUMP : std_logic;
signal sMPX_BUS_O : std_logic_vector(0 to 8);
signal P_1050_SEL_OUT : STD_LOGIC;
signal P_1050_SEL_IN : STD_LOGIC;
signal n1050_REQ_IN : STD_LOGIC;
signal n1050_CE_MODE : STD_LOGIC;
signal MPX_OPN_LT_GATE : STD_LOGIC;
signal ADDR_OUT : STD_LOGIC;
-- Outputs from UDC3 (5-10A through 5-14D)
signal A_BUS3 : STD_LOGIC_VECTOR(0 to 8);
signal SEL_WR_CALL : STD_LOGIC := '0';
signal SX1_SHARE_CYCLE : STD_LOGIC := '0';
signal SX2_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_AUX_WR_CALL : STD_LOGIC := '0';
signal SEL_AUX_RD_CALL : STD_LOGIC := '0';
signal SEL_CONV_OSC : STD_LOGIC;
signal SEL_BASIC_CLOCK_OFF : STD_LOGIC;
signal SEL_SHARE_HOLD : STD_LOGIC := '0';
signal SEL_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_CHNL_DATA_XFER : STD_LOGIC := '0';
signal SEL_ROS_REQ : STD_LOGIC := '0';
signal SEL_READ_CALL : STD_LOGIC := '0';
signal SEL_RD_WR_CTRL : STD_LOGIC := '0';
signal SEL_RD_CALL_TO_STP : STD_LOGIC := '0';
signal SEL_CC_ROS_REQ : STD_LOGIC := '0';
signal MAN_DSPLY_GUV_HUV : STD_LOGIC := '0';
signal HSMPX_TRAP : STD_LOGIC := '0';
signal n1050_SEL_O : STD_LOGIC;
signal n1050_INSTALLED : STD_LOGIC;
signal n1050_OP_IN : STD_LOGIC;
-- Inputs to UDC3
signal SEL_DATA_READY : STD_LOGIC;
signal SEL_CHNL_CPU_CLOCK_STOP : STD_LOGIC;
signal RST_SEL_CHNL_DIAG_LCHS : STD_LOGIC;
signal LOAD_REQ_LCH : STD_LOGIC;
signal USE_GR_OR_HR : STD_LOGIC;
signal SX_CHAIN_PULSE_1 : STD_LOGIC;
signal CHK_RST_SW : STD_LOGIC;
signal S : std_logic_vector(0 to 7);
signal sM_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : std_logic;
signal MACH_RST_2A,MACH_RST_2B,MACH_RST_3, MACH_RST_6 : std_logic;
signal CARRY_0 : STD_LOGIC;
signal COMPLEMENT,NTRUE : STD_LOGIC;
signal FT0,FT1,FT2,FT3,FT5,FT6,FT7 : STD_LOGIC;
signal M_ASSM_BUS1, N_ASSM_BUS1 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS2, N_ASSM_BUS2 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS3, N_ASSM_BUS3 : STD_LOGIC_VECTOR(0 to 8);
signal N1050_INTRV_REQ : STD_LOGIC := '0';
signal TT6_POS_ATTN : STD_LOGIC := '0';
-- signal FT2_MPX_OPNL : STD_LOGIC := '0';
signal MPX_METERING_IN,METER_IN_SX1,METER_IN_SX2 : STD_LOGIC;
signal KEY_SW : STD_LOGIC;
signal GT_SWS_TO_WX_PWR : STD_LOGIC;
signal GT_MAN_SET_MN : STD_LOGIC;
signal EXT_TRAP_MASK_ON : STD_LOGIC;
signal MANUAL_STORE,MAN_STOR_OR_DSPLY : STD_LOGIC;
signal RECYCLE_RST : STD_LOGIC;
signal T_REQUEST : STD_LOGIC := '0';
signal MACH_RST_SET_LCH : STD_LOGIC;
signal RST_LOAD : STD_LOGIC;
signal CARRY_0_LCHD,CARRY_1_LCHD : STD_LOGIC;
signal ALU_CHK : STD_LOGIC;
signal CTRL_N,N_CTRL_LM : STD_LOGIC;
signal SX1_RD_CYCLE,SX2_RD_CYCLE : STD_LOGIC;
signal SX1_WR_CYCLE,SX2_WR_CYCLE : STD_LOGIC;
signal GT_DETECTORS_TO_HR : STD_LOGIC;
signal CPU_RD_PWR : STD_LOGIC;
signal XH,XL,XXH : STD_LOGIC;
signal SET_FW : STD_LOGIC;
signal keyboard_data : STD_LOGIC_VECTOR(7 downto 0);
signal keyboard_error : STD_LOGIC;
signal USE_MANUAL_DECODER : STD_LOGIC;
signal sUSE_MAN_DECODER_PWR : STD_LOGIC;
signal LOCAL_STORAGE_CP, MAIN_STORAGE_CP : STD_LOGIC;
signal STACK_RD_WR_CONTROL : STD_LOGIC;
signal H_REG_5_PWR : STD_LOGIC;
signal FORCE_M_REG_123 : STD_LOGIC;
signal N_SEL_SHARE_HOLD : STD_LOGIC;
signal GK,HK : STD_LOGIC_VECTOR(0 to 3);
signal PROT_LOC_CPU_OR_MPX : STD_LOGIC;
signal PROT_LOC_SEL_CHNL : STD_LOGIC;
signal EARLY_M_REG_0 : STD_LOGIC;
signal ODD : STD_LOGIC; -- 06B to 04A
signal SUPPR_A_REG_CHK : STD_LOGIC;
signal STATUS_IN_LCHD : STD_LOGIC;
signal M_REG_0 : STD_LOGIC;
signal SYS_RST_PRIORITY_LCH : STD_LOGIC;
signal STORE_R : STD_LOGIC;
signal SAL_PC : STD_LOGIC;
signal R_REG_PC : STD_LOGIC;
signal N2ND_ERROR_STOP : STD_LOGIC;
signal MEM_WRAP : STD_LOGIC;
signal MACH_RST_PROT : STD_LOGIC;
signal MACH_RST_MPX : STD_LOGIC;
signal GM_WM_DETECTED : STD_LOGIC;
signal FIRST_MACH_CHK_REQ : STD_LOGIC;
signal FIRST_MACH_CHK : STD_LOGIC;
signal DECIMAL : STD_LOGIC;
signal INTRODUCE_ALU_CHK : STD_LOGIC;
signal SERV_IN_LCHD, ADDR_IN_LCHD, OPNL_IN_LCHD : STD_LOGIC;
signal MPX_SHARE_REQ, MPX_INTERRUPT : STD_LOGIC;
signal CS_DECODE_X001 : STD_LOGIC;
signal SX1_INTERRUPT, SX2_INTERRUPT : STD_LOGIC;
signal SX_1_GATE, SX_2_GATE : STD_LOGIC;
signal SX_1_R_W_CTRL, SX_2_R_W_CTRL : STD_LOGIC;
signal SX_2_BUMP_SW_GT : STD_LOGIC;
-- signal FT3_MPX_SHARE_REQ : STD_LOGIC;
signal CONNECT : STD_LOGIC;
signal P_8F_DETECTED : STD_LOGIC;
signal BASIC_CS0 : STD_LOGIC;
signal USE_R : STD_LOGIC;
signal ANY_MACH_CHK : STD_LOGIC;
signal USE_MAIN_MEMORY, USE_LOCAL_MAIN_MEMORY : STD_LOGIC;
signal ALLOW_PROTECT : STD_LOGIC;
signal USE_BASIC_CA_DECO, USE_ALT_CA_DECODER : STD_LOGIC;
signal ALLOW_PC_SALS : STD_LOGIC;
signal SUPPR_MACH_CHK_TRAP : STD_LOGIC;
signal N1401_MODE : STD_LOGIC;
signal MEM_PROTECT_REQUEST : STD_LOGIC;
signal MANUAL_DISPLAY : STD_LOGIC;
signal MAIN_STORAGE : STD_LOGIC;
signal MACH_RST_SET_LCH_DLY : STD_LOGIC;
signal MACH_RST_SW : STD_LOGIC;
signal MACH_CHK_RST : STD_LOGIC;
signal MACH_CHK_PULSE : STD_LOGIC;
signal GT_D_REG_TO_A_BUS : STD_LOGIC;
signal GT_CA_TO_W_REG : STD_LOGIC;
signal DATA_READY : STD_LOGIC;
signal CTRL_REG_CHK : STD_LOGIC;
signal CPU_WRITE_IN_R_REG : STD_LOGIC;
signal CPU_SET_ALLOW_WR_LCH : STD_LOGIC;
signal ANY_PRIORITY_LCH : STD_LOGIC;
signal ALLOW_WRITE_DLYD : STD_LOGIC;
signal ALLOW_WRITE : STD_LOGIC;
signal STORE_HR : STD_LOGIC;
signal STORE_GR : STD_LOGIC;
signal SEL_R_W_CTRL : STD_LOGIC;
signal SEL_CHNL_CHK : STD_LOGIC;
signal HR_REG_0_7, GR_REG_0_7 : STD_LOGIC_VECTOR(0 to 7);
signal STORE_BITS : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal HR_REG_P_BIT : STD_LOGIC;
signal GR_REG_P_BIT : STD_LOGIC;
signal GT_DETECTORS_TO_GR : STD_LOGIC;
signal EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : STD_LOGIC;
signal CHANNEL_RD_CALL : STD_LOGIC;
signal MPX_ROS_LCH : STD_LOGIC;
signal CK_SAL_P_BIT_TO_MPX : STD_LOGIC;
signal STG_MEM_SEL : STD_LOGIC;
signal GATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal CLOCK_START_LCH : STD_LOGIC;
signal LOAD_IND : STD_LOGIC;
signal CLOCK_OUT : STD_LOGIC;
signal READ_ECHO_1, READ_ECHO_2, WRITE_ECHO_1, WRITE_ECHO_2 : STD_LOGIC;
signal DIAGNOSTIC_SW : STD_LOGIC;
signal A_BUS, sFI : STD_LOGIC_VECTOR(0 to 8);
begin
firstBit: entity udc1 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
WX_IND => WX_IND,
X_IND_P => X_IND_P,
W_IND_P => W_IND_P,
A_BUS => A_BUS1,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
MPX_BUS => sFI,
S => S,
R => R,
MN => MN,
M_ASSM_BUS => M_ASSM_BUS1,
N_ASSM_BUS => N_ASSM_BUS1,
SW_START => SW_START,
SW_LOAD => SW_LOAD,
SW_SET_IC => SW_SET_IC,
SW_STOP => SW_STOP,
SW_INH_CF_STOP => SW_INH_CF_STOP,
SW_PROC => SW_PROC,
SW_SCAN => SW_SCAN,
SW_SINGLE_CYCLE => SW_SINGLE_CYCLE,
SW_INSTRUCTION_STEP => SW_INSTRUCTION_STEP,
SW_RATE_SW_PROCESS => SW_RATE_SW_PROCESS,
SW_PWR_OFF => SW_POWER_OFF,
SW_LAMP_TEST => SW_LAMP_TEST,
SW_DSPLY => SW_DSPLY,
SW_STORE => SW_STORE,
SW_SYS_RST => SW_SYS_RST,
SW_CHK_RST => SW_CHK_RST,
SW_ROAR_RST => SW_ROAR_RST,
SW_CHK_RESTART => SW_CHK_RESTART,
SW_DIAGNOSTIC => SW_DIAGNOSTIC,
SW_CHK_STOP => SW_CHK_STOP,
SW_CHK_SW_PROCESS => SW_CHK_SW_PROCESS,
SW_CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
SW_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SW_ROAR_RESTT => SW_ROAR_RESTT,
SW_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
SW_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
SW_ROAR_STOP => SW_ROAR_STOP,
SW_ROAR_SYNC => SW_ROAR_SYNC,
SW_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
SW_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
SW_SAR_STOP => SW_SAR_STOP,
SW_SAR_RESTART => SW_SAR_RESTART,
SW_INTRP_TIMER => SW_INTRP_TIMER,
SW_CONS_INTRP => SW_CONS_INTRP,
SW_A => SW_A,SW_B => SW_B,SW_C => SW_C,SW_D => SW_D,
SW_F => SW_F,SW_G => SW_G,SW_H => SW_H,SW_J => SW_J,
SW_AP => SW_AP,SW_BP => SW_BP,SW_CP => SW_CP,SW_DP => SW_DP,
SW_FP => SW_FP,SW_GP => SW_GP,SW_HP => SW_HP,SW_JP => SW_JP,
TO_KEY_SW => TO_KEY_SW,
E_SW => E_SW, -- Main E switch bus
IND_SYST => IND_SYST,
IND_MAN => IND_MAN,
IND_WAIT => IND_WAIT,
IND_TEST => IND_TEST,
IND_LOAD => IND_LOAD,
IND_EX => IND_EX,
IND_CY_MATCH => IND_CY_MATCH,
IND_ALLOW_WR => IND_ALLOW_WR,
IND_1050_INTRV => IND_1050_INTRV,
IND_1050_REQ => IND_1050_REQ,
IND_MPX => IND_MPX,
IND_SEL_CHNL => IND_SEL_CHNL,
IND_MSDR => IND_MSDR,
IND_MSDR_P => IND_MSDR_P,
CARRY_0 => CARRY_0,
CARRY_0_LCHD => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
COMPLEMENT => COMPLEMENT,
NTRUE => NTRUE,
MPX_METERING_IN => MPX_METERING_IN,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
METER_IN_SX1 => METER_IN_SX1,
METER_IN_SX2 => METER_IN_SX2,
KEY_SW => KEY_SW,
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE,
N1050_INTRV_REQ => N1050_INTRV_REQ,
GT_1050_TAGS => GT_1050_TAGS,
GT_1050_BUS => GT_1050_BUS,
TT6_POS_ATTN => TT6_POS_ATTN,
FT2_MPX_OPNL => FT2,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
FT0 => FT0,
FT1 => FT1,
FT2 => FT2,
FT3 => FT3,
FT5 => FT5,
FT6 => FT6,
FT7 => FT7,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
ALU_CHK => ALU_CHK,
CTRL_N => CTRL_N,
N_CTRL_N => N_CTRL_N,
N_CTRL_LM => N_CTRL_LM,
STORE_S_REG_RST => STORE_S_REG_RST,
MAIN_STORAGE_CP => MAIN_STORAGE_CP,
LOCAL_STORAGE_CP => LOCAL_STORAGE_CP,
SET_IND_ROSAR => SET_IND_ROSAR,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_TO_MN_REG => GT_T_REG_TO_MN,
GT_CK_TO_MN_REG => GT_CK_TO_MN,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
PROT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
WX_CHK => WX_CHK,
EARLY_M_REG_0 => EARLY_M_REG_0,
ODD => ODD,
XH => XH,
XL => XL,
XXH => XXH,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
M_REG_0 => M_REG_0,
SYS_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
STORE_R => STORE_R,
SAL_PC => SAL_PC,
R_REG_PC => R_REG_PC,
RST_LOAD => RST_LOAD,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
MACH_RST_PROT => MACH_RST_PROT,
MACH_RST_MPX => MACH_RST_MPX,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
GM_WM_DETECTED => GM_WM_DETECTED,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
DECIMAL => DECIMAL,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MPX_SHARE_REQ => MPX_SHARE_REQ,
MPX_INTERRUPT => MPX_INTERRUPT,
CS_DECODE_X001 => CS_DECODE_X001,
CLOCK_OFF => CLOCK_OFF,
CONNECT => CONNECT,
P_8F_DETECTED => P_8F_DETECTED,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALU_CHK_LCH => ALU_CHK_LCH,
ALLOW_PROTECT => ALLOW_PROTECT,
ALLOW_PC_SALS => ALLOW_PC_SALS,
USE_R => USE_R,
USE_BASIC_CA_DECODER => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SEL => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STORAGE => MAIN_STORAGE,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WRITE_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE => ALLOW_WRITE,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
GT_MAN_SET_MN => GT_MAN_SET_MN,
MPX_ROS_LCH => MPX_ROS_LCH,
CTRL_REG_RST => CTRL_REG_RST,
CK_SAL_P_BIT_TO_MPX => CK_SAL_P_BIT_TO_MPX,
CHANNEL_RD_CALL => CHANNEL_RD_CALL,
GTD_CA_BITS => GATED_CA_BITS,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_MAIN_MEMORY => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
SELECT_CPU_BUMP => SELECT_CPU_BUMP,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
CPU_RD_PWR => CPU_RD_PWR,
LOAD_IND => LOAD_IND,
SET_FW => SET_FW,
MACH_RST_SW => MACH_RST_SW,
LOAD_REQ_LCH => LOAD_REQ_LCH,
USE_GR_OR_HR => USE_GR_OR_HR,
SX_CHAIN_PULSE_1 => SX_CHAIN_PULSE_1,
CHK_RST_SW => CHK_RST_SW,
DIAGNOSTIC_SW => DIAGNOSTIC_SW,
MAN_DSPLY_GUV_HUV => MAN_DSPLY_GUV_HUV,
HSMPX_TRAP => HSMPX_TRAP,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SX_1_R_W_CTRL => SX_1_R_W_CTRL,
SX_2_R_W_CTRL => SX_2_R_W_CTRL,
SX_2_BUMP_SW_GT => SX_2_BUMP_SW_GT,
SEL_WR_CALL => SEL_WR_CALL,
SEL_AUX_WR_CALL => SEL_AUX_WR_CALL,
SEL_AUX_RD_CALL => SEL_AUX_RD_CALL,
SEL_T1 => SEL_T1,
SEL_T4 => SEL_T4,
SEL_CONV_OSC => SEL_CONV_OSC,
SEL_BASIC_CLOCK_OFF => SEL_BASIC_CLOCK_OFF,
SEL_SHARE_HOLD => SEL_SHARE_HOLD,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_CHNL_DATA_XFER => SEL_CHNL_DATA_XFER,
SEL_ROS_REQ => SEL_ROS_REQ,
SEL_READ_CALL => SEL_READ_CALL,
SEL_RD_WR_CTRL => SEL_RD_WR_CTRL,
SEL_RD_CALL_TO_STP => SEL_RD_CALL_TO_STP,
SEL_CHNL_CPU_CLOCK_STOP => SEL_CHNL_CPU_CLOCK_STOP,
RST_SEL_CHNL_DIAG_LCHS => RST_SEL_CHNL_DIAG_LCHS,
SEL_CC_ROS_REQ => SEL_CC_ROS_REQ,
SX1_INTERRUPT => SX1_INTERRUPT,
SX2_INTERRUPT => SX2_INTERRUPT,
SX_1_GATE => SX_1_GATE,
SX_2_GATE => SX_2_GATE,
CLOCK_ON => CLOCK_ON,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_START => CLOCK_START,
CLOCK_START_LCH => CLOCK_START_LCH,
-- UDC1 Debug stuff
DEBUG => open,
-- End of Debug stuff
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P4 => P4,
CLK => CLK
);
IND_SALS <= sSALS;
USE_MAN_DECODER_PWR <= sUSE_MAN_DECODER_PWR;
secondBit: entity udc2 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
A_BUS1 => A_BUS,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
E_BUS => E_SW,
M_ASSM_BUS => M_ASSM_BUS2,
N_ASSM_BUS => N_ASSM_BUS2,
S => S,
R => R,
MN => MN,
Sw_Slow => SwSlow,
CLOCK_START => CLOCK_START,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
CLOCK_IN => clk,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_ON => CLOCK_ON,
LAMP_TEST => SW_LAMP_TEST,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
DIAG_SW => DIAGNOSTIC_SW,
CHK_SW_PROC_SW => SW_CHK_SW_PROCESS,
ROS_SCAN => SW_SCAN,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
RST_LOAD => RST_LOAD,
SYSTEM_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
CARRY_0_LATCHED => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
ALU_CHK => ALU_CHK,
NTRUE => NTRUE,
COMPLEMENT => COMPLEMENT,
P_CTRL_N => CTRL_N,
N_CTRL_LM => N_CTRL_LM,
SX1_RD_CYCLE => SX1_RD_CYCLE,
SX2_RD_CYCLE => SX2_RD_CYCLE,
SX1_WR_CYCLE => SX1_WR_CYCLE,
SX2_WR_CYCLE => SX2_WR_CYCLE,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
CPU_RD_PWR => CPU_RD_PWR,
GT_MAN_SET_MN => GT_MAN_SET_MN,
CHNL_RD_CALL => CHANNEL_RD_CALL,
XH => XH,
XL => XL,
XXH => XXH,
MAN_STOR_PWR => MANUAL_STORE,
STORE_S_REG_RST => STORE_S_REG_RST,
E_SW_SEL_S => E_SW.S_SEL,
CTRL_REG_RST => CTRL_REG_RST,
CLOCK_OFF => CLOCK_OFF,
A_REG_PC => A_REG_PC,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
P_CONNECT => CONNECT,
N_CTRL_N => N_CTRL_N,
ALU_CHK_LCH => ALU_CHK_LCH,
MN_PC => MN_PC,
SET_IND_ROSAR => SET_IND_ROSAR,
N_STACK_MEMORY_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_REG_TO_MN => GT_T_REG_TO_MN, -- from 05B
GT_CK_TO_MN => GT_CK_TO_MN,
MAIN_STG_CP_1 => MAIN_STORAGE_CP,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
SEL_CPU_BUMP => SELECT_CPU_BUMP,
PROTECT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
PROTECT_LOC_SEL_CHNL => PROT_LOC_SEL_CHNL,
WX_CHK => WX_CHK,
EARLY_M0 => EARLY_M_REG_0,
ODD => ODD,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
STORE_R => STORE_R,
SALS_PC => SAL_PC,
R_REG_PC => R_REG_PC,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
USE_R => USE_R,
USE_MAIN_MEM => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SELECT => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STG => MAIN_STORAGE,
MACH_RST_SW => MACH_RST_SW,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
LOCAL_STG => LOCAL_STORAGE_CP,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WR_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
ALLOW_WRITE => ALLOW_WRITE,
T_REQUEST => T_REQUEST,
P_8F_DETECTED => P_8F_DETECTED,
CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
GATED_CA_BITS => GATED_CA_BITS,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALLOW_PC_SALS => ALLOW_PC_SALS,
CARRY_0 => CARRY_0,
ALLOW_PROTECT => ALLOW_PROTECT,
CS_DECODE_X001 => CS_DECODE_X001,
DECIMAL => DECIMAL,
M_REG_0 => M_REG_0,
MACH_RST_PROT => MACH_RST_PROT,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
MPX_ROS_LCH => MPX_ROS_LCH,
FT7 => FT7,
FT6 => FT6,
FT5 => FT5,
FT2 => FT2,
FT0 => FT0,
FT3 => FT3,
MPX_INTERRUPT => MPX_INTERRUPT,
MPX_METERING_IN => MPX_METERING_IN,
STORE_BITS => STORE_BITS,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MACH_RST_MPX => MACH_RST_MPX,
SET_FW => SET_FW,
MPX_SHARE_REQ => MPX_SHARE_REQ,
LOAD_IND => LOAD_IND,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
-- Signals from UDC3
N_SEL_SHARE_HOLD => N_SEL_SHARE_HOLD, -- from 12D
GK => GK, -- from 11B
HK => HK, -- from 13B
STORE_HR => STORE_HR,
STORE_GR => STORE_GR,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_R_W_CTRL => SEL_R_W_CTRL,
SEL_CHNL_CHK => SEL_CHNL_CHK,
HR_REG_0_7 => HR_REG_0_7,
GR_REG_0_7 => GR_REG_0_7,
HR_REG_P_BIT => HR_REG_P_BIT,
GR_REG_P_BIT => GR_REG_P_BIT,
GT_HSMPX_INTO_R_REG => '0',
DR_CORR_P_BIT => '0',
GT_DETECTORS_TO_HR => GT_DETECTORS_TO_HR,
GT_DETECTORS_TO_GR => GT_DETECTORS_TO_GR,
EVEN_HR_0_7_BITS => EVEN_HR_0_7_BITS,
EVEN_GR_0_7_BITS => EVEN_GR_0_7_BITS,
ADDR_OUT => ADDR_OUT,
-- Indicators
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
IND_CHK_A_REG => IND_CHK_A_REG,
IND_CHK_B_REG => IND_CHK_B_REG,
IND_CHK_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_CHK_CTRL_REG => IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS => IND_CHK_ROS_SALS,
IND_CHK_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_CHK_STOR_DATA => IND_CHK_STOR_DATA,
IND_CHK_ALU => IND_CHK_ALU,
-- Selector & Mpx channels
MPX_BUS_O => sMPX_BUS_O,
MPX_BUS_I => MPX_BUS_I,
MPX_TAGS_O => MPX_TAGS_O,
MPX_TAGS_I => MPX_TAGS_I,
FI => sFI,
MPX_OPN_LT_GATE => MPX_OPN_LT_GATE,
n1050_SEL_O => n1050_SEL_O,
P_1050_SEL_OUT => P_1050_SEL_OUT,
P_1050_SEL_IN => P_1050_SEL_IN,
n1050_INSTALLED => n1050_INSTALLED,
n1050_REQ_IN => n1050_REQ_IN,
n1050_OP_IN => n1050_OP_IN,
n1050_CE_MODE => n1050_CE_MODE,
StorageIn => StorageIn,
StorageOut => StorageOut,
-- UDC2 Debug stuff
DEBUG => open,
SEL_T1 => SEL_T1,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
SEL_T3 => SEL_T3,
Clk => Clk
);
thirdBit : entity udc3 (FMD) port map (
-- Inputs
E_SW_SEL_BUS => E_SW,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
GTD_CA_BITS => GATED_CA_BITS,
Z_BUS => Z_BUS,
GT_1050_TAGS_OUT => GT_1050_TAGS,
GT_1050_BUS_OUT => GT_1050_BUS,
-- PCH_CONN_ENTRY => PCH_CONN_ENTRY,
P_1050_SEL_OUT => P_1050_SEL_OUT,
P_1050_SEL_IN => P_1050_SEL_IN,
n1050_OP_IN => n1050_OP_IN,
SUPPRESS_OUT => FT0,
CK_SAL_P_BIT => CK_SAL_P_BIT_TO_MPX,
MPX_OPN_LT_GATE => MPX_OPN_LT_GATE,
RECYCLE_RESET => RECYCLE_RST,
-- Outputs
A_BUS => A_BUS3,
M_ASSM_BUS => M_ASSM_BUS3,
N_ASSM_BUS => N_ASSM_BUS3,
T_REQUEST => T_REQUEST,
-- RDR_1_CONN_EXIT => RDR_1_CONN_EXIT,
-- n1050_CONTROL => n1050_CONTROL,
N1050_INTRV_REQ => N1050_INTRV_REQ,
TT6_POS_ATTN => TT6_POS_ATTN,
n1050_SEL_O => n1050_SEL_O,
n1050_INSTALLED => n1050_INSTALLED,
n1050_REQ_IN => n1050_REQ_IN,
n1050_CE_MODE => n1050_CE_MODE,
ADDR_OUT => ADDR_OUT,
SerialInput => SerialInput,
SerialOutput => SerialOutput,
-- Clocks
clk => clk,
Clock1ms => Clock1ms,
Clock60Hz => N60_CY_TIMER_PULSE,
-- UDC3 debug
DEBUG => DEBUG,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4
);
M_CONV_OSC <= sM_CONV_OSC;
-- Temporary substitutes for UDC3
SEL_CONV_OSC <= P_CONV_OSC; -- 12A
SEL_BASIC_CLOCK_OFF <= not CLOCK_ON and not CLOCK_START_LCH; -- 12A
-- Combining buses
M_ASSM_BUS2 <= M_ASSM_BUS1 or M_ASSM_BUS3;
N_ASSM_BUS2 <= N_ASSM_BUS1 or N_ASSM_BUS3;
A_BUS <= A_BUS1 and A_BUS3;
end FMD;

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---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030-storage.vhd
-- Creation Date: 19:55:00 20/07/10
-- Description:
-- 360/30 Storage Handling - Main and Local (Bump) Storage
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-20
-- Revision 1.1 2012-03-06 Modified to parse PCH files from Hercules (ESD/TXT/TXT/TXT/RLD/RLD/END)
-- Initial Release
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity storage is
Port ( -- Physical storage I/O from FPGA
phys_address : out std_logic_vector(16 downto 0);
phys_data : inout std_logic_vector(8 downto 0);
phys_CE : out std_logic;
phys_OE : out std_logic;
phys_WE : out std_logic;
phys_UB,phys_LB : out std_logic;
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
-- Interface to config ROM
din : in STD_LOGIC;
reset_prom : out STD_LOGIC;
cclk : out STD_LOGIC;
-- Storage interface to CPU
StorageIn : out STORAGE_IN_INTERFACE;
StorageOut : in STORAGE_OUT_INTERFACE;
debug : out STD_LOGIC
);
end storage;
architecture Behavioral of storage is
--
-- declaration of serial configuration PROM reading interface
--
component prom_reader_serial
generic( length : integer := 5; --sync pattern 2^length
frequency : integer := 50 ); --system clock speed in MHz
port( clock : in std_logic;
reset : in std_logic; --active high
read : in std_logic; --active low single cycle pulse
next_sync : in std_logic; --active low single cycle pulse
din : in std_logic;
sync_pattern : in std_logic_vector((2**length) - 1 downto 0);
cclk : out std_logic;
sync : out std_logic; --active low single cycle pulse
data_ready : out std_logic; --active low single cycle pulse
reset_prom : out std_logic; --active high to /OE of PROM (reset when high)
dout : out std_logic_vector(7 downto 0));
end component;
-- Signals for RAM clearing and initialisation purposes (at startup)
signal drive_out : std_logic;
signal addr : std_logic_vector(15 downto 0) := "0000000000000000";
signal len : std_logic_vector(15 downto 0) := "0000000000000000";
signal init_CE : std_logic;
signal init_WE : std_logic;
signal init_OE : std_logic;
signal init_drive_out, clear_data_out, clear_local_data_out, init_data_out: std_logic;
signal clear_data : std_logic_vector(7 downto 0) := "00000000"; -- Value written into storage locations when clearing
signal init_data : std_logic_vector(7 downto 0);
type init_state is (
initClearMainStorage,initClearLocalStorage,
resetProm,resetProm2,
wait_for_first_high_length_byte,wait_for_high_length_byte,got_high_length_byte,wait_for_low_length_byte,got_low_length_byte,
wait_for_high_address_byte,got_high_address_byte,wait_for_low_address_byte,got_low_address_byte,
wait_for_data_byte, write_byte, written_byte, finished);
signal state : init_state := initClearMainStorage;
--
-- Signals for serial PROM reader
--
signal reset_prom_reader : std_logic;
signal prom_read_pulse : std_logic;
signal prom_sync_pulse : std_logic;
signal prom_data_ready_pulse : std_logic;
begin
-- See Xilinx XAPP694 for how to store user data in the platform flash
-- Input file format is
-- Header 8F9FAFBF (see XAPP694)
-- LL High byte of data segment length
-- LL Low byte of data segment length
-- AA High byte of destination address
-- AA Low byte of destination address
-- DD Data byte (repeated a total of LLLL times)
-- LL LL AA AA DD DD ... DD repeated as required
-- 00 00 Length of 0000 to terminate
Initialise: process(clk) is
begin
-- Initialise storage
if clk'event and clk='1' then -- Wait for rising edge of 50MHz clock
case state is
-- Clear the 64k of main storage space
when initClearMainStorage =>
init_data_out <= '0'; -- '1' if we're initialising RAM from PROM
clear_data_out <= '1'; -- '1' if we're clearing the 64k main storage space
clear_local_data_out <= '0'; -- '1' if we're clearing the local storage space
addr <= (others=>'0'); -- Start clearing at 0000
len <= (others=>'0'); -- Clear 64k
state <= write_byte; -- Will come back to initClearLocalStorage
-- Clear 64k of local storage space, though only a small portion is actually used
when initClearLocalStorage =>
clear_data_out <= '0'; -- Done with clearing main storage...
clear_local_data_out <= '1'; -- ... so on to clearing local storage
addr <= (others=>'0'); -- Start clearing at 0000
len <= (others=>'0'); -- Clear 64k
state <= write_byte; -- Will come back to resetProm
when resetProm =>
clear_data_out <= '0'; -- Done with clearing main storage...
clear_local_data_out <= '0'; -- ...and local storage...
init_data_out <= '1'; -- ...so on to initialising storage from PROM
state <= resetProm2;
when resetProm2 =>
state <= wait_for_first_high_length_byte;
when wait_for_first_high_length_byte =>
-- Wait until we get the first data byte, which is the high byte of the length
-- Note we don't need to assert the PROM read pulse in this state
-- as the first byte following the sync pattern is automatically read
if (prom_data_ready_pulse = '0') then
len(15 downto 8) <= init_data;
state <= got_high_length_byte;
else
state <= wait_for_high_length_byte;
end if;
when wait_for_high_length_byte =>
-- Wait until we get a high length byte
if (prom_data_ready_pulse = '0') then
-- Store it in len (high)
len(15 downto 8) <= init_data;
state <= got_high_length_byte;
else
state <= wait_for_high_length_byte;
end if;
when got_high_length_byte =>
state <= wait_for_low_length_byte;
when wait_for_low_length_byte =>
-- Wait until we get a low length byte
if (prom_data_ready_pulse = '0') then
-- Store it in len (low)
len(7 downto 0) <= init_data;
-- Check if both bytes are 00, finish if so
-- Note: Can't check len(7 downto 0) as it isn't in there yet
if len(15 downto 8)="00000000" and init_data="00000000" then
state <= finished;
else
-- Not 0 length, go on to getting address & data bytes
state <= got_low_length_byte;
end if;
else
state <= wait_for_low_length_byte;
end if;
when got_low_length_byte =>
state <= wait_for_high_address_byte;
when wait_for_high_address_byte =>
-- Wait until we get the high address byte
if (prom_data_ready_pulse = '0') then
-- Store it in addr (high)
addr(15 downto 8) <= init_data;
state <= got_high_address_byte;
else
state <= wait_for_high_address_byte;
end if;
when got_high_address_byte =>
prom_read_pulse <= '0';
state <= wait_for_low_address_byte;
when wait_for_low_address_byte =>
-- Wait until we get the low address byte
if (prom_data_ready_pulse = '0') then
-- Store it in addr (low)
addr(7 downto 0) <= init_data;
state <= got_low_address_byte;
else
state <= wait_for_low_address_byte;
end if;
when got_low_address_byte =>
state <= wait_for_data_byte;
when wait_for_data_byte =>
-- Wait until we get one of our data bytes from the PROM
if (prom_data_ready_pulse = '0') then
state <= write_byte;
else
state <= wait_for_data_byte;
end if;
when write_byte =>
-- WE* is asserted during this state and does the actual write
state <= written_byte;
when written_byte =>
-- Bump address and count
addr <= addr + "0000000000000001";
len <= len - "0000000000000001";
-- Compare length to 1 (not 0) as it is about to be decremented
if (len="0000000000000001") then
-- Ok, have done all the bytes now
if clear_data_out='1' then
-- If we were clearing main storage, go on to clearing local storage
state <= initClearLocalStorage;
else if clear_local_data_out='1' then
-- If we were clearing local storage, go on to initialising storage
state <= resetProm;
else
-- Doing initialisation, so look for a further length value
state <= wait_for_high_length_byte;
end if;
end if;
else
-- Not finished yet
if clear_data_out='1' or clear_local_data_out='1' then
-- Clearing storage can go straight back and do another byte
state <= write_byte;
else
-- Initialising storage needs to fetch a byte from PROM
state <= wait_for_data_byte;
end if;
end if;
when finished =>
-- Make sure we can't interfere with CPU operation
init_data_out <= '0';
when others =>
end case;
end if;
end process;
-- Outputs generated as a function of the initialisation machine state:
init_drive_out <= '0' when state=finished else '1';
init_ce <= '0' when state=wait_for_data_byte or state=write_byte or state=written_byte else '1';
init_oe <= '1';
init_we <= '0' when state=write_byte else '1'; -- Only assert WE* from the one state
reset_prom_reader <= '1' when state=resetProm or state=resetProm2 else '0';
-- reset_prom_reader <= '1' when state=resetProm else '0';
prom_read_pulse <= '0' when state=wait_for_high_length_byte
or state=wait_for_low_length_byte
or state=wait_for_high_address_byte
or state=wait_for_low_address_byte
or state=wait_for_data_byte; -- Trigger a further PROM read when in these states
phys_CE <= init_ce when init_drive_out='1' else '0' when StorageOut.ReadPulse='1' or StorageOut.WritePulse='1' else '1'; -- Select which CE* to use
phys_WE <= init_we when init_drive_out='1' else '0' when StorageOut.WritePulse='1' else '1'; -- Select which WE* to use
phys_UB <= '0'; -- Always select upper byte
phys_LB <= '0'; -- Always select lower byte
phys_OE <= init_oe when init_drive_out='1' else '0' when StorageOut.ReadPulse='1' or StorageOut.WritePulse='0' else '1'; -- Assert OE* if reading
drive_out <= '1' when init_drive_out='1' else '0' when StorageOut.ReadPulse='1' else '1'; -- Whether data bus is driving out, or tristated for input
-- Read in and latch data when doing a real memory read (note - this does not erase the memory as real core would)
StorageIn.ReadData <= phys_data when StorageOut.ReadPulse='1';
-- Select initialisation data or real (R reg) data to go out when writing
phys_data <= init_data & evenParity(init_data) when init_drive_out='1' and init_data_out='1'
else clear_data & evenParity(clear_data) when init_drive_out='1' and (clear_data_out='1' or clear_local_data_out='1')
else StorageOut.WriteData when drive_out='1'
else "ZZZZZZZZZ";
-- Select initialisation address or real (MN reg) address to go out
-- Top bit is 0 for Local Storage and 1 for Main Storage
phys_address <= (not clear_local_data_out) & addr when init_drive_out='1' else StorageOut.MainStorage & StorageOut.MSAR;
-- This turns the debug light on during initialisation
-- (if configured in the higher-level blocks)
debug <= init_drive_out;
--
----------------------------------------------------------------------------------------------------------------------------------
-- Serial configuration PROM reader
----------------------------------------------------------------------------------------------------------------------------------
--
-- This macro enables data stored afater the Spartan-3 configuration data to be located and then read
-- sequentially.
--
prom_access: prom_reader_serial
generic map( length => 5, --Synchronisation pattern is 2^5 = 32 bits
frequency => 50) --System clock rate is 50MHz
port map( clock => clk,
reset => reset_prom_reader, --reset reader and initiates search for sync pattern
read => prom_read_pulse, --active low pulse initiates retrieval of next byte
next_sync => '1', --would be used to find another sync pattern
din => din, --from XCF04S device
sync_pattern => X"8F9FAFBF", --32bit synchronisation pattern is constant in this application
cclk => cclk, --to XCF04S device
sync => prom_sync_pulse, --active low pulse indicates sync pattern located
data_ready => prom_data_ready_pulse, --active low pulse indicates data byte received
reset_prom => reset_prom, --to XCF04S device
dout => init_data); --byte received from serial prom
end behavioral;

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---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030-switches.vhd
-- Creation Date: 21:49:37 20/01/2010
-- Description:
-- 360/30 Front Panel switch handling
-- Some switches are provided by the pushbuttons and sliders on the S3BOARD
-- Rotary switches are connected externally with a mixture of scanning and
-- discrete inputs. In all cases the "Process" position is not connected so
-- omitting the switches entirely allows the system to run normally.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.01 2010-07-20
-- [LJW] Add Switch connection information, no functional change
--
--
-- Func Port Pin Conn A2 A B C D E F G H J AC E' ROS Rate Check
-- Ground 1 - - - - - - - - - - - - - -
-- +5V 2 - - - - - - - - - - - - - -
-- +3.3V Vcco 3 - - - - - - - - - - C C C C
-- Hex0 pa_io1 E6 4 * * * * * * * * * # - - - -
-- Hex1 pa_io2 D5 5 * * * * * * * * * # - - - -
-- Hex2 pa_io3 C5 6 * * * * * * * * * # - - - -
-- Hex3 pa_io4 D6 7 * * * * * * * * * # - - - -
-- ScanA pa_io5 C6 8 S - - - - - - - - - - - - -
-- ScanB pa_io6 E7 9 - S - - - - - - - - - - - -
-- ScanC pa_io7 C7 10 - - S - - - - - - - - - - -
-- ScanD pa_io8 D7 11 - - - S - - - - - - - - - -
-- ScanE pa_io9 C8 12 - - - - S - - - - - - - - -
-- ScanF pa_io10 D8 13 - - - - - S - - - - - - - -
-- ScanG pa_io11 C9 14 - - - - - - S - - - - - - -
-- ScanH pa_io12 D10 15 - - - - - - - S - - - - - -
-- ScanJ pa_io13 A3 16 - - - - - - - - S - - - - -
-- ScanAC pa_io14 B4 17 - - - - - - - - - S - - - -
-- E_Inner pa_io15 A4 18 - - - - - - - - - - * - - -
-- E_Outer pa_io16 B5 19 - - - - - - - - - - * - - -
-- ROS InhCFStop pa_io17 A5 20 - - - - - - - - - - - * - -
-- ROS Scan pa_io18 B6 21 - - - - - - - - - - - * - -
-- Rate_InstrStep ma2_db0 B7 22 - - - - - - - - - - - - * -
-- Rate_SingleCyc ma2_db1 A7 23 - - - - - - - - - - - - * -
-- Check_Diag ma2_db2 B8 24 - - - - - - - - - - - - - *
-- Check_Disable ma2_db3 A8 25 - - - - - - - - - - - - - *
-- Check_Stop ma2_db4 A9 26 - - - - - - - - - - - - - *
-- Check_Restart ma2_db5 B10 27 - - - - - - - - - - - - - *
--
-- * = Hex0,1,2,3 inputs have diodes from each of the 9 hex-encoded switches A-J (A to switch, K to FPGA, total 36 diodes)
-- # = The Address Compare switch (AC) is 10-position, unencoded, with diodes to perform the 0-9 encoding (total 15 diodes)
-- S = Scan output to switch common (one output at a time goes high to scan)
-- C = Common connection for non-scanned switches
-- Switch E' is the selector switch which is part of switch E and selects the inner, middle or outer rings
-- The "Proc" positions of the ROS, Rate and Check switches are not connected - if no switches are present then these 3 and the AC switch default to "Proc"
-- The "Middle" position of the E selector switch is not connected - the default is therefore the MS/LS ring
-- Pulldowns are provided by the FPGA input
--
-- Most of the remaining switches are connected to the on-board pushbuttons and slide switches:
-- Reset
-- Start
-- Stop
-- Load
-- Lamp Test
-- ROAR Reset
-- Display
-- Store
-- Check Reset
-- Set IC
-- Interrupt
-- Fast/Slow clock control
-- Two switches are not used:
-- Power Off
-- Timer Interrupt
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.EvenParity;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity switches is
Port ( -- Raw switch inputs: (These can be modified to suit the board being used)
SwA_scan : out STD_LOGIC;
SwB_scan : out STD_LOGIC;
SwC_scan : out STD_LOGIC;
SwD_scan : out STD_LOGIC;
SwE_scan : out STD_LOGIC;
SwF_scan : out STD_LOGIC;
SwG_scan : out STD_LOGIC;
SwH_scan : out STD_LOGIC;
SwJ_scan : out STD_LOGIC;
SwAC_scan : out STD_LOGIC; -- Address Compare
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
SW_E_Inner, SW_E_Outer : in STD_LOGIC;
RawSw_Proc_Inh_CF_Stop, RawSw_Proc_Scan : in STD_LOGIC; -- ROS Control
RawSw_Rate_Single_Cycle, RawSw_Rate_Instruction_Step : in STD_LOGIC; -- Rate
RawSw_Chk_Chk_Restart, RawSw_Chk_Diagnostic, RawSw_Chk_Stop, RawSw_Chk_Disable : in STD_LOGIC; -- Check Control
pb : in std_logic_vector(3 downto 0); -- On-board pushbuttons
sw : in std_logic_vector(7 downto 0); -- On-board slide switches
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
-- Conditioned switch outputs:
SwA,SwB,SwC,SwD,SwF,SwG,SwH,SwJ : out STD_LOGIC_VECTOR(3 downto 0);
SwAP,SwBP,SwCP,SwDP,SwFP,SwGP,SwHP,SwJP : out STD_LOGIC;
SwE : out E_SW_BUS_Type;
Sw_PowerOff, Sw_Interrupt, Sw_Load : out STD_LOGIC; -- Right-hand pushbuttons
Sw_SystemReset, Sw_RoarReset, Sw_Start, Sw_SetIC, Sw_CheckReset,
Sw_Stop, Sw_IntTmr, Sw_Store, Sw_LampTest, Sw_Display : out STD_LOGIC; -- Left-hand pushbuttons
Sw_Proc_Inh_CF_Stop, Sw_Proc_Proc, Sw_Proc_Scan : out STD_LOGIC; -- ROS Control
Sw_Rate_Single_Cycle, Sw_Rate_Instruction_Step, Sw_Rate_Process : out STD_LOGIC; -- Rate
Sw_Chk_Chk_Restart, Sw_Chk_Diagnostic, Sw_Chk_Stop, Sw_Chk_Process, Sw_Chk_Disable : out STD_LOGIC; -- Check Control
Sw_ROAR_RESTT,Sw_ROAR_RESTT_WITHOUT_RST,Sw_EARLY_ROAR_STOP,Sw_ROAR_STOP, Sw_ROAR_RESTT_STOR_BYPASS,
Sw_ROAR_SYNC,Sw_ADDR_COMP_PROC,Sw_SAR_DLYD_STOP,Sw_SAR_STOP,Sw_SAR_RESTART : out STD_LOGIC; -- Address Compare
-- 1kHz clock signal
Clock1ms : out STD_LOGIC;
-- 50Hz Timer signal
Timer : out STD_LOGIC
);
end switches;
architecture Behavioral of switches is
subtype debounce is std_logic_vector(0 to 3);
signal scan : std_logic_vector(3 downto 0) := "0000";
signal counter : std_logic_vector(14 downto 0) := (others=>'0');
signal counter1k : std_logic_vector(15 downto 0) := (others=>'0');
signal timerCounter : std_logic_vector(5 downto 0) := (others=>'0');
signal SwE_raw : std_logic_vector(3 downto 0) := "0000";
signal SwAC : std_logic_vector(3 downto 0) := "0000"; -- Address Compare switch
signal Parity_in : std_logic;
signal RawSw_PowerOff, RawSw_Interrupt, RawSw_Load, RawSw_SystemReset, RawSw_RoarReset, RawSw_Start,
RawSw_SetIC, RawSw_CheckReset, RawSw_Stop, RawSw_IntTmr, RawSw_Store, RawSw_LampTest,
RawSw_Display : STD_LOGIC; -- Right-hand pushbuttons
signal debouncePowerOff, debounceInterrupt, debounceLoad,
debounceSystemReset, debounceRoarReset, debounceStart, debounceSetIC, debounceCheckReset,
debounceStop, debounceIntTmr, debounceStore, debounceLampTest, debounceDisplay : debounce;
signal timerOut : std_logic := '0';
signal sClock1ms : std_logic := '0';
constant divider : std_logic_vector(14 downto 0) := "100111000100000"; -- 20,000 gives 2.5kHz
constant divider2000 : std_logic_vector(14 downto 0) := "110000110101000"; -- 25,000 gives 2kHz
constant sample : std_logic_vector(14 downto 0) := "100111000011110"; -- 19,999
constant divider100 : std_logic_vector(4 downto 0) := "11001"; --- 25 converts 2.5kHz to 100Hz for timer
begin
Parity_in <= EvenParity(Hex_in);
scan_counter: process(clk)
begin
if (rising_edge(clk)) then
if counter=sample then
if scan="0000" then SwA <= Hex_in; SwAP <= Parity_in; end if;
if scan="0001" then SwB <= Hex_in; SwBP <= Parity_in; end if;
if scan="0010" then SwC <= Hex_in; SwCP <= Parity_in; end if;
if scan="0011" then SwD <= Hex_in; SwDP <= Parity_in; end if;
if scan="0100" then SwE_raw <= Hex_in; end if;
if scan="0101" then SwF <= Hex_in; SwFP <= Parity_in; end if;
if scan="0110" then SwG <= Hex_in; SwGP <= Parity_in; end if;
if scan="0111" then SwH <= Hex_in; SwHP <= Parity_in; end if;
if scan="1000" then SwJ <= Hex_in; SwJP <= Parity_in; end if;
if scan="1001" then SwAC <= Hex_in; end if;
end if;
if counter=divider then
counter<=(others=>'0');
if scan="1001" then
scan <= "0000";
else
scan <= scan + 1;
end if;
debouncePowerOff <= debouncePowerOff(1 to 3) & rawSw_PowerOff;
debounceInterrupt <= debounceInterrupt(1 to 3) & rawSw_Interrupt;
debounceLoad <= debounceLoad(1 to 3) & rawSw_Load;
debounceSystemReset <= debounceSystemReset(1 to 3) & rawSw_SystemReset;
debounceRoarReset <= debounceRoarReset(1 to 3) & rawSw_RoarReset;
debounceStart <= debounceStart(1 to 3) & rawSw_Start;
debounceSetIC <= debounceSetIC(1 to 3) & rawSw_SetIC;
debounceCheckReset <= debounceCheckReset(1 to 3) & rawSw_CheckReset;
debounceStop <= debounceStop(1 to 3) & rawSw_Stop;
debounceIntTmr <= debounceIntTmr(1 to 3) & rawSw_IntTmr;
debounceStore <= debounceStore(1 to 3) & rawSw_Store;
debounceLampTest <= debounceLampTest(1 to 3) & rawSw_LampTest;
debounceDisplay <= debounceDisplay(1 to 3) & rawSw_Display;
if (debouncePowerOff = "0000") then Sw_PowerOff <= '0'; else if (debouncePowerOff = "1111") then Sw_PowerOff <= '1'; end if; end if;
if (debounceInterrupt = "0000") then Sw_Interrupt <= '0'; else if (debounceInterrupt = "1111") then Sw_Interrupt <= '1'; end if; end if;
if (debounceLoad = "0000") then Sw_Load <= '0'; else if (debounceLoad = "1111") then Sw_Load <= '1'; end if; end if;
if (debounceSystemReset = "0000") then Sw_SystemReset <= '0'; else if (debounceSystemReset = "1111") then Sw_SystemReset <= '1'; end if; end if;
if (debounceRoarReset = "0000") then Sw_RoarReset <= '0'; else if (debounceRoarReset = "1111") then Sw_RoarReset <= '1'; end if; end if;
if (debounceStart = "0000") then Sw_Start <= '0'; else if (debounceStart = "1111") then Sw_Start <= '1'; end if; end if;
if (debounceSetIC = "0000") then Sw_SetIC <= '0'; else if (debounceSetIC = "1111") then Sw_SetIC <= '1'; end if; end if;
if (debounceCheckReset = "0000") then Sw_CheckReset <= '0'; else if (debounceCheckReset = "1111") then Sw_CheckReset <= '1'; end if; end if;
if (debounceStop = "0000") then Sw_Stop <= '0'; else if (debounceStop = "1111") then Sw_Stop <= '1'; end if; end if;
if (debounceIntTmr = "0000") then Sw_IntTmr <= '0'; else if (debounceIntTmr = "1111") then Sw_IntTmr <= '1'; end if; end if;
if (debounceStore = "0000") then Sw_Store <= '0'; else if (debounceStore = "1111") then Sw_Store <= '1'; end if; end if;
if (debounceLampTest = "0000") then Sw_LampTest <= '0'; else if (debounceLampTest = "1111") then Sw_LampTest <= '1'; end if; end if;
if (debounceDisplay = "0000") then Sw_Display <= '0'; else if (debounceDisplay = "1111") then Sw_Display <= '1'; end if; end if;
if (timerCounter = divider100) then
timerOut <= not timerOut;
Timer <= timerOut;
timerCounter <= (others=>'0');
else
timerCounter <= timerCounter + 1;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
Clock1kHz : process(clk)
begin
if (rising_edge(clk)) then
if counter1k = divider2000 then
counter1k <= (others => '0');
sClock1ms <= not sClock1ms;
else
counter1k <= counter1k + 1;
end if;
end if;
end process;
Clock1ms <= sClock1ms;
SwA_scan <= '1' when scan="0000" else '0';
SwB_scan <= '1' when scan="0001" else '0';
SwC_scan <= '1' when scan="0010" else '0';
SwD_scan <= '1' when scan="0011" else '0';
SwE_scan <= '1' when scan="0100" else '0';
SwF_scan <= '1' when scan="0101" else '0';
SwG_scan <= '1' when scan="0110" else '0';
SwH_scan <= '1' when scan="0111" else '0';
SwJ_scan <= '1' when scan="1000" else '0';
SwAC_scan <= '1' when scan="1001" else '0';
-- Inner ring
SwE.I_SEL <= '1' when SwE_raw="0000" and SW_E_INNER='1' else '0';
SwE.J_SEL <= '1' when SwE_raw="0001" and SW_E_INNER='1' else '0';
SwE.U_SEL <= '1' when SwE_raw="0010" and SW_E_INNER='1' else '0';
SwE.V_SEL <= '1' when SwE_raw="0011" and SW_E_INNER='1' else '0';
SwE.L_SEL <= '1' when SwE_raw="0100" and SW_E_INNER='1' else '0';
SwE.T_SEL <= '1' when SwE_raw="0101" and SW_E_INNER='1' else '0';
SwE.D_SEL <= '1' when SwE_raw="0110" and SW_E_INNER='1' else '0';
SwE.R_SEL <= '1' when SwE_raw="0111" and SW_E_INNER='1' else '0';
SwE.S_SEL <= '1' when SwE_raw="1000" and SW_E_INNER='1' else '0';
SwE.G_SEL <= '1' when SwE_raw="1001" and SW_E_INNER='1' else '0';
SwE.H_SEL <= '1' when SwE_raw="1010" and SW_E_INNER='1' else '0';
SwE.FI_SEL <= '1' when SwE_raw="1011" and SW_E_INNER='1' else '0';
SwE.FT_SEL <= '1' when SwE_raw="1100" and SW_E_INNER='1' else '0';
-- Mid ring
SwE.MS_SEL <= '1' when SwE_raw="0000" and SW_E_INNER='0' and SW_E_OUTER='0' else '0';
SwE.LS_SEL <= '1' when SwE_raw="0001" and SW_E_INNER='0' and SW_E_OUTER='0' else '0';
-- Outer ring
SwE.E_SEL_SW_GS <= '1' when SwE_raw="0000" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_GT <= '1' when SwE_raw="0001" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_GUV_GCD <= '1' when SwE_raw="0010" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_HS <= '1' when SwE_raw="0011" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_HT <= '1' when SwE_raw="0100" and SW_E_OUTER='1' else '0';
SwE.E_SEL_SW_HUV_HCD <= '1' when SwE_raw="0101" and SW_E_OUTER='1' else '0';
SwE.Q_SEL <= '1' when SwE_raw="0110" and SW_E_OUTER='1' else '0';
SwE.C_SEL <= '1' when SwE_raw="0111" and SW_E_OUTER='1' else '0';
SwE.F_SEL <= '1' when SwE_raw="1000" and SW_E_OUTER='1' else '0';
SwE.TT_SEL <= '1' when SwE_raw="1001" and SW_E_OUTER='1' else '0';
SwE.TI_SEL <= '1' when SwE_raw="1010" and SW_E_OUTER='1' else '0';
SwE.JI_SEL <= '1' when SwE_raw="1011" and SW_E_OUTER='1' else '0';
-- SwE.IJ_SEL <= '1' when (SwE_raw="0000" or SwE_raw="0001") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- SwE.UV_SEL <= '1' when (SwE_raw="0010" or SwE_raw="0011") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- Address Compare
Sw_ADDR_COMP_PROC <= '1' when SwAC="0000" else '0';
Sw_SAR_DLYD_STOP <= '1' when SwAC="0001" else '0';
Sw_SAR_STOP <= '1' when SwAC="0010" else '0';
Sw_SAR_RESTART <= '1' when SwAC="0011" else '0';
Sw_ROAR_RESTT_STOR_BYPASS <= '1' when SwAC="0100" else '0';
Sw_ROAR_RESTT <= '1' when SwAC="0101" else '0';
Sw_ROAR_RESTT_WITHOUT_RST <= '1' when SwAC="0110" else '0';
Sw_EARLY_ROAR_STOP <= '1' when SwAC="0111" else '0';
Sw_ROAR_STOP <= '1' when SwAC="1000" else '0';
Sw_ROAR_SYNC <= '1' when SwAC="1001" else '0';
-- ROS Control
Sw_Proc_Inh_CF_Stop <= '1' when RawSw_Proc_Inh_CF_Stop='1' else '0';
Sw_Proc_Proc <= '1' when RawSw_Proc_Inh_CF_Stop='0' and RawSw_Proc_Scan='0' else '0';
Sw_Proc_Scan <= '1' when RawSw_Proc_Scan='1' else '0';
-- Rate
Sw_Rate_Single_Cycle <= '1' when RawSw_Rate_Single_Cycle='1' else '0';
Sw_Rate_Process <= '1' when RawSw_Rate_Single_Cycle='0' and RawSw_Rate_Instruction_Step='0' else '0';
Sw_Rate_Instruction_Step <= '1' when RawSw_Rate_Instruction_Step='1' else '0';
-- Check Control
Sw_Chk_Chk_Restart <= '1' when RawSw_Chk_Chk_Restart='1' else '0';
Sw_Chk_Diagnostic <= '1' when RawSw_Chk_Diagnostic='1' else '0';
Sw_Chk_Stop <= '1' when RawSw_Chk_Stop='1' else '0';
Sw_Chk_Process <= '1' when RawSw_Chk_Chk_Restart='0' and RawSw_Chk_Diagnostic='0' and RawSw_Chk_Stop='0' and RawSw_Chk_Disable='0' else '0';
Sw_Chk_Disable <= '1' when RawSw_Chk_Disable='1' else '0';
-- Unimplemented switches
RawSw_PowerOff <= '0';
RawSw_IntTmr <= '0';
-- Pushbuttons
RawSw_SystemReset <= pb(0);
RawSw_Start <= pb(1);
RawSw_Load <= pb(2);
RawSw_Stop <= pb(3);
-- Slide switches
RawSw_Display <= sw(1);
RawSw_Store <= sw(2);
RawSw_Interrupt <= sw(3);
RawSw_RoarReset <= sw(4);
RawSw_SetIC <= sw(5);
RawSw_CheckReset <= sw(6);
RawSw_LampTest <= sw(7);
end behavioral;

194
ibm2030-vga.vhd
View File

@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -34,8 +34,8 @@
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
-- Revision 1.1 2012-04-07
-- Add Multiplexor Tag indicators
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
@ -87,7 +87,7 @@ constant screen : screenType :=
" ***** ",
" ",
" TAGS BUS OUT ",
" ********* P84218421 ",
" stuvwxyz{ P84218421 ",
" MSAR a ",
" P84218421 P84218421 b ",
" MSDR ALU STAT CHKS ",
@ -155,7 +155,7 @@ constant indLayout : screenIndicators :=
-- To convert ASCII to the internal 6-bit representation...
-- Not all characters are needed, so some special ones are added
subtype characterCode is std_logic_vector(6 downto 0);
type charArray is array(character'(' ') to character'('z')) of characterCode;
type charArray is array(character'(' ') to character'('{')) of characterCode;
constant charTranslate : charArray := (
-- 20->62, 21 ! ->61, 22-23->127, 24->59, 25-29->127, 2A->60, 2B-2F->127
"0111110","0111101","1111111","1111111","0111011","1111111","1111111","1111111",
@ -174,9 +174,9 @@ constant charTranslate : charArray := (
-- 61 a to 6F o -> 63 to 77
"0111111","1000000","1000001","1000010","1000011","1000100","1000101","1000110",
"1000111","1001000","1001001","1001010","1001011","1001100","1001101",
-- 70 p to 7A z -> 78 to 88
-- 70 p to 7A z -> 78 to 88, 7B { -> 89
"1001110","1001111","1010000","1010001","1010010","1010011","1010100","1010101",
"1010110","1010111","1011000"
"1010110","1010111","1011000","1011001"
);
-- Character bitmaps
@ -1270,6 +1270,186 @@ constant characterGenerator : characterGeneratorType :=
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
81 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00110011100100101000",
"01001010010110101000",
"01001011100111101000",
"01001010000101101000",
"00110010000100101111",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
82 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00110011100111001110",
"01001010010100101001",
"01111010010100101110",
"01001010010100101010",
"01001011100111101001",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
83 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111011100110011100",
"01000001001001001000",
"00110001001111001000",
"00001001001001001000",
"01110001001001001000",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
84 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111011110111001001",
"01000010000100101001",
"00110011100111001001",
"00001010000101000110",
"01110011110100100110",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
85 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00001110111101000000",
"00010000100001000000",
"00001100111001000000",
"00000010100001000000",
"00011110111101111000",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
86 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00110011100111001110",
"01001010010100101001",
"01111010010100101110",
"01001010010100101010",
"01001011100111101001",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
87 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111010010100101110",
"01000011110111101001",
"01000010010100101001",
"01000010010100101001",
"00111010010100101110",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
88 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111011110111001001",
"01000010000100101001",
"00110011100111001001",
"00001010000101000110",
"01110011110100100110",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
89 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111010010111001110",
"01000010010100101001",
"00110010010111001110",
"00001010010100001000",
"01110011110100001000",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
others => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",

119
ibm2030.vhd
View File

@ -1,5 +1,5 @@
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson lawrence@ljw.me.uk
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
@ -34,7 +34,9 @@
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial release - no I/O
--
-- Revision 1.1 2012-04-07
-- 1050 Serial console added
-- External main and aux storage, with pre-loading from platform flash
--
---------------------------------------------------------------------------
library IEEE;
@ -48,21 +50,53 @@ use work.all;
entity ibm2030 is
Port ( -- Physical I/O on Digilent S3 Board
-- Seven-segment displays
-- ssd : out std_logic_vector(7 downto 0); -- 7-segment segment cathodes (not used)
-- ssdan : out std_logic_vector(3 downto 0); -- 7-segment digit anodes (not used)
led : out std_logic_vector(7 downto 0); -- 8 LEDs
-- ssdan : out std_logic_vector(3 downto 0); -- 7-segment digit anodes (not used)
-- Discrete LEDs
led : out std_logic_vector(7 downto 0); -- 8 LEDs
-- Pushbuttons and switches
pb : in std_logic_vector(3 downto 0); -- 4 pushbuttons
sw : in std_logic_vector(7 downto 0); -- 8 slide switches
sw : in std_logic_vector(7 downto 0); -- 8 slide switches
-- Connections to scanned front panel switches
pa_io1,pa_io2,pa_io3,pa_io4 : in std_logic := '0'; -- 4 digital inputs
pa_io5,pa_io6,pa_io7,pa_io8,pa_io9,
pa_io10,pa_io11,pa_io12,pa_io13,pa_io14 : out std_logic; -- 10 digital switch scanning outputs
pa_io15,pa_io16,pa_io17,pa_io18,ma2_db0,ma2_db1,
ma2_db2,ma2_db3,ma2_db4,ma2_db5: in std_logic := '0'; -- 10 digital switch scan inputs
-- ma2_db6,ma2_db7,ma2_astb,ma2_dstb,ma2_write, ma2_wait, ma2_reset, ma2_int : in std_logic := '0'; -- 8 digital inputs (not used)
-- ps2_clk : inout std_logic; -- Keyboard/Mouse clock (not used)
-- ps2_data : inout std_logic; -- Keyboard/Mouse data (not used)
vga_r,vga_g,vga_b,vga_hs,vga_vs : out std_logic; -- VGA output RGB+Sync
clk : in std_logic);
-- ma2_db6,ma2_db7,ma2_astb,ma2_dstb,ma2_write, ma2_wait, ma2_reset, ma2_int : in std_logic := '0'; -- 8 digital inputs (not used)
-- Keyboard connection
-- ps2_clk : inout std_logic; -- Keyboard/Mouse clock (not used)
-- ps2_data : inout std_logic; -- Keyboard/Mouse data (not used)
-- Video output
vga_r,vga_g,vga_b,vga_hs,vga_vs : out std_logic; -- VGA output RGB+Sync
-- Static RAM interface
sramaddr : out std_logic_vector(17 downto 0);
srama : inout std_logic_vector(8 downto 0);
sramace : out std_logic;
sramwe : out std_logic;
sramoe : out std_logic;
sramaub : out std_logic;
sramalb : out std_logic;
-- Serial I/O
serialRx : in std_logic;
serialTx : out std_logic := '1';
-- 50Mhz clock
clk : in std_logic;
-- Configuration PROM interface
din : in std_logic;
reset_prom : out std_logic;
rclk : out std_logic);
end ibm2030;
architecture FMD of ibm2030 is
@ -123,12 +157,23 @@ signal SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : STD_LOGIC;
signal E_SW : E_SW_BUS_Type;
-- Misc stuff
signal StorageIn : STORAGE_IN_INTERFACE; -- CPU interface to storage
signal StorageOut : STORAGE_OUT_INTERFACE; -- CPU interface to storage
signal SerialIn : PCH_CONN;
signal SerialOut : RDR_CONN;
signal SerialControl : CONN_1050;
signal SerialBusUngated : STD_LOGIC_VECTOR(7 downto 0);
signal RxDataAvailable : STD_LOGIC;
signal RxAck, PunchGate : STD_LOGIC;
signal SO : Serial_Output_Lines;
signal SwSlow : STD_LOGIC := '0'; -- Set to '1' to slow clock down to 1Hz, not used
signal N60_CY_TIMER_PULSE : STD_LOGIC; -- Used for the Interval Timer
signal Clock1ms : STD_LOGIC; -- 1kHz clock for single-shots etc.
signal DEBUG : STD_LOGIC := '0'; -- Spare variable for debug purposes
signal DEBUG : DEBUG_BUS; -- Passed to all modeles to probe signals
begin
cpu : entity cpu port map (
@ -230,6 +275,18 @@ begin
SW_JP => SW_JP,
E_SW => E_SW,
-- Storage interface
StorageIn => StorageIn,
StorageOut => StorageOut,
-- Serial interface for 1050
serialInput.SerialRx => SerialRx,
serialInput.DCD => '1',
serialInput.DSR => '1',
serialInput.RI => '0',
serialInput.CTS => '1',
serialOutput => SO,
-- Multiplexor interface not connected to anything yet
MPX_BUS_O => open,
MPX_BUS_I => (others=>'0'),
@ -238,6 +295,7 @@ begin
DEBUG => DEBUG, -- Used to pass debug signals up to the top level for output
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE, -- Actually 50Hz
Clock1ms => Clock1ms,
SwSlow => SwSlow,
clk => clk -- 50Mhz clock
);
@ -343,7 +401,7 @@ begin
led(4) <= IND_SYST;
led(5) <= '0';
led(6) <= '0';
led(7) <= DEBUG;
led(7) <= DEBUG.Probe;
frontPanel_switches: entity switches port map (
-- Hardware switch inputs and scan outputs
@ -420,8 +478,41 @@ begin
Sw_SAR_RESTART => SW_SAR_RESTART,
-- Clocks etc.
clk => clk, -- 50MHz clock
clk => clk, -- 50MHz clock
Clock1ms => Clock1ms,
Timer => N60_CY_TIMER_PULSE -- Output from Switches is actually 50Hz
);
core_storage : entity storage port map(
phys_address => sramaddr(16 downto 0),
phys_data => srama(8 downto 0),
phys_CE => sramace,
phys_OE => sramoe,
phys_WE => sramwe,
phys_UB => sramaub,
phys_LB => sramalb,
-- Interface to config ROM
din => din,
reset_prom => reset_prom,
cclk => rclk,
-- Storage interface to CPU
StorageIn => StorageIn,
StorageOut => StorageOut,
-- Debug => Debug,
-- Other inputs
clk => clk
);
sramaddr(17) <= '0';
DEBUG.Selection <= CONV_INTEGER(unsigned(SW_J));
SerialTx <= SO.SerialTx;
-- with DEBUG.Selection select
-- DEBUG.Probe <=
-- SerialBusUngated(0) when 0, SerialBusUngated(1) when 1, SerialBusUngated(2) when 2, SerialBusUngated(3) when 3,
-- SerialBusUngated(4) when 4, SerialBusUngated(5) when 5, SerialBusUngated(6) when 6, SerialBusUngated(7) when 7,
-- RxDataAvailable when others;
end FMD;

193
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@ -0,0 +1,193 @@
--*****************************************************************************************
--**
--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
--** provided to you "as is". Xilinx and its licensors make and you
--** receive no warranties or conditions, express, implied, statutory
--** or otherwise, and Xilinx specifically disclaims any implied
--** warranties of merchantability, non-infringement, or fitness for a
--** particular purpose. Xilinx does not warrant that the functions
--** contained in these designs will meet your requirements, or that the
--** operation of these designs will be uninterrupted or error free, or
--** that defects in the Designs will be corrected. Furthermore, Xilinx
--** does not warrant or make any representations regarding use or the
--** results of the use of the designs in terms of correctness, accuracy,
--** reliability, or otherwise.
--**
--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
--** liable for any loss of data, lost profits, cost or procurement of
--** substitute goods or services, or for any special, incidental,
--** consequential, or indirect damages arising from the use or operation
--** of the designs or accompanying documentation, however caused and on
--** any theory of liability. This limitation will apply even if Xilinx
--** has been advised of the possibility of such damage. This limitation
--** shall apply not-withstanding the failure of the essential purpose of
--** any limited remedies herein.
--**
--*****************************************************************************************
-- MODULE : shift_compare_serial.vhd
-- AUTHOR : Stephan Neuhold
-- VERSION : v1.00
--
--
-- REVISION HISTORY:
-- -----------------
-- No revisions
--
--
-- FUNCTION DESCRIPTION:
-- ---------------------
-- This module provides the shifting in of data
-- and comparing that data to the synchronisation
-- pattern. Once the synchronisation pattern has
-- been found, the last eight bits of data
-- shifted in are presented.
--
-- The shift register and comparator are
-- automatically scaled to the correct length
-- using the "length" generic.
--***************************
--* Library declarations
--***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--***********************
--* Entity declaration
--***********************
entity shift_compare_serial is
generic(
length : integer := 5
);
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
din : in std_logic;
b : in std_logic_vector((2**length) - 1 downto 0);
eq : out std_logic;
din_shifted : out std_logic_vector(7 downto 0)
);
end shift_compare_serial;
architecture Behavioral of shift_compare_serial is
signal q : std_logic_vector((2**length) - 1 downto 0);
signal r : std_logic_vector((2**length) downto 0);
signal a : std_logic_vector((2**length) - 1 downto 0);
signal b_swapped : std_logic_vector((2**length) - 1 downto 0);
signal GND : std_logic;
begin
--***************************************************
--* This process swaps the bits in the data byte.
--* This is done to present the data in the format
--* that it is entered in the PROM file.
--***************************************************
process (clock, a)
begin
for i in 0 to 7 loop
din_shifted(i) <= a(((2**length) - 1) - i);
end loop;
end process;
--*******************************************************
--* This process swaps the bits of every byte of the
--* synchronisation pattern. This is done so that
--* data read in from the PROM can be directly
--* compared. Data from the PROM is read with all
--* bits of every byte swapped.
--* e.g.
--* If the data in the PROM is 28h then this is read in
--* the following way:
--* 00010100
--*******************************************************
process (clock, b)
begin
for i in 0 to (((2**length) / 8) - 1) loop
for j in 0 to 7 loop
b_swapped((8 * i) + j) <= b(7 + (8 * i) - j);
end loop;
end loop;
end process;
--***********************************************
--* This is the first FF of the shift register.
--* It needs to be seperated from the rest
--* since it has a different input.
--***********************************************
GND <= '0';
r(0) <= '1';
Data_Shifter_0_Serial: FDRE
port map(
C => clock,
D => din,
CE => enable,
R => reset,
Q => a(0)
);
--***************************************************
--* This loop generates as many registers needed
--* based on the length of the synchronisation
--* word.
--***************************************************
Shifter_Serial:
for i in 1 to (2**length) - 1 generate
Data_Shifter_Serial: FDRE
port map(
C => clock,
D => a(i - 1),
CE => enable,
R => reset,
Q => a(i)
);
end generate;
--***********************************************
--* This loop generates as many LUTs and MUXCYs
--* as needed based on the length of the
--* synchronisation word.
--***********************************************
Comparator_Serial:
for i in 0 to (2**length) - 1 generate
Comparator_LUTs_Serial: LUT2
generic map(
INIT => X"9"
)
port map(
I0 => a(i),
I1 => b_swapped(i),
O => q(i)
);
Comparator_MUXs_Serial: MUXCY
port map(
DI => GND,
CI => r(i),
S => q(i),
O => r(i + 1)
);
end generate;
eq <= r(2**length);
end Behavioral;

239
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@ -0,0 +1,239 @@
------------------------------------------------------------------------
-- vga_controller_640_60.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic to generate the synchronization signals,
-- horizontal and vertical pixel counter and video disable signal
-- for the 640x480@60Hz resolution.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web regarding the
-- vga video timings:
-- http://www.epanorama.net/documents/pc/vga_timing.html
-- This module generates the video synch pulses for the monitor to
-- enter 640x480@60Hz resolution state. It also provides horizontal
-- and vertical counters for the currently displayed pixel and a blank
-- signal that is active when the pixel is not inside the visible screen
-- and the color outputs should be reset to 0.
-- timing diagram for the horizontal synch signal (HS)
-- 0 648 744 800 (pixels)
-- -------------------------|______|-----------------
-- timing diagram for the vertical synch signal (VS)
-- 0 482 484 525 (lines)
-- -----------------------------------|______|-------
-- The blank signal is delayed one pixel clock period (40ns) from where
-- the pixel leaves the visible screen, according to the counters, to
-- account for the pixel pipeline delay. This delay happens because
-- it takes time from when the counters indicate current pixel should
-- be displayed to when the color data actually arrives at the monitor
-- pins (memory read delays, synchronization delays).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- rst - global reset signal
-- pixel_clk - input pin, from dcm_25MHz
-- - the clock signal generated by a DCM that has
-- - a frequency of 25MHz.
-- HS - output pin, to monitor
-- - horizontal synch pulse
-- VS - output pin, to monitor
-- - vertical synch pulse
-- hcount - output pin, 11 bits, to clients
-- - horizontal count of the currently displayed
-- - pixel (even if not in visible area)
-- vcount - output pin, 11 bits, to clients
-- - vertical count of the currently active video
-- - line (even if not in visible area)
-- blank - output pin, to clients
-- - active when pixel is not in visible area.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the vga_controller_640_60 entity declaration
-- read above for behavioral description and port definitions.
entity vga_controller_640_60 is
port(
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
hcount : out std_logic_vector(10 downto 0);
vcount : out std_logic_vector(10 downto 0);
hchar : out std_logic_vector(10 downto 0);
vchar : out std_logic_vector(10 downto 0);
hpixel : out std_logic_vector(5 downto 0);
vpixel : out std_logic_vector(5 downto 0);
blank : out std_logic
);
end vga_controller_640_60;
architecture Behavioral of vga_controller_640_60 is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- number of horizontal pixels per character
constant HPIX : std_logic_vector(5 downto 0) := "010011"; -- 19
-- number of vertical pixels per character
constant VPIX : std_logic_vector(5 downto 0) := "010011"; -- 19
-- maximum value for the horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- maximum value for the vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01000001101"; -- 525
-- total number of visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01010000000"; -- 640
-- value for the horizontal counter where front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01010001000"; -- 648
-- value for the horizontal counter where the synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01011101000"; -- 744
-- total number of visible lines
constant VLINES: std_logic_vector(10 downto 0) := "00111100000"; -- 480
-- value for the vertical counter where the front porch ends
constant VFP : std_logic_vector(10 downto 0) := "00111100010"; -- 482
-- value for the vertical counter where the synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "00111100100"; -- 484
-- polarity of the horizontal and vertical synch pulse
-- only one polarity used, because for this resolution they coincide.
constant SPP : std_logic := '0';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- horizontal and vertical counters
signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
signal hch : std_logic_vector(10 downto 0) := (others => '0');
signal vch : std_logic_vector(10 downto 0) := (others => '0');
signal hpx : std_logic_vector(5 downto 0) := (others => '0');
signal vpx : std_logic_vector(5 downto 0) := (others => '0');
-- active when inside visible screen area.
signal video_enable: std_logic;
begin
-- output horizontal and vertical counters
hcount <= hcounter;
vcount <= vcounter;
hpixel <= hpx;
vpixel <= vpx;
hchar <= hch;
vchar <= vch;
-- blank is active when outside screen visible area
-- color output should be blacked (put on 0) when blank in active
-- blank is delayed one pixel clock period from the video_enable
-- signal to account for the pixel pipeline delay.
blank <= not video_enable when rising_edge(pixel_clk);
-- increment horizontal counter at pixel_clk rate
-- until HMAX is reached, then reset and keep counting
h_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
hcounter <= (others => '0');
hch <= (others => '0');
hpx <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
hch <= (others => '0');
hpx <= (others => '0');
else
hcounter <= hcounter + 1;
if(hpx=HPIX) then
hpx <= (others => '0');
hch <= hch + 1;
else
hpx <= hpx + 1;
end if;
end if;
end if;
end process h_count;
-- increment vertical counter when one line is finished
-- (horizontal counter reached HMAX)
-- until VMAX is reached, then reset and keep counting
v_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
vcounter <= (others => '0');
vch <= (others => '0');
vpx <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
vch <= (others => '0');
vpx <= (others => '0');
else
vcounter <= vcounter + 1;
if(vpx=VPIX) then
vpx <= (others => '0');
vch <= vch + 1;
else
vpx <= vpx + 1;
end if;
end if;
end if;
end if;
end process v_count;
-- generate horizontal synch pulse
-- when horizontal counter is between where the
-- front porch ends and the synch pulse ends.
-- The HS is active (with polarity SPP) for a total of 96 pixels.
do_hs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
-- when vertical counter is between where the
-- front porch ends and the synch pulse ends.
-- The VS is active (with polarity SPP) for a total of 2 video lines
-- = 2*HMAX = 1600 pixels.
do_vs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
-- enable video output when pixel is in visible area
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
end Behavioral;